tag: known good die

Speeding Up Metrology At Advanced Nodes
By Gregory Haley - 11 Jun, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk metrology at the most advanced nodes and the impact of using different substrates, with Frank Chen, director of applications and product management at Bruker Nano Surfaces & Metrology; John Hoffman, computer vision engineering manager at Nordson Test & Measurement; and Jiangtao Hu, senior technology director at Onto Inn... » read more

Rebalancing Test And Yield In IC Manufacturing
By Gregory Haley - 07 Nov, 2023 - Comments: 0

Balancing yield and test is essential to semiconductor manufacturing, but it's becoming harder to determine how much weight to give one versus the other as chips become more specialized for different applications. Yield focuses on maximizing the number of functional chips from a production batch, while test aims to ensure that each chip meets rigorous quality and performance standards. And w... » read more

Manual X-ray Inspection
By Ed Sperling - 28 Aug, 2023 - Comments: 0

Increased density in advanced node chips and advanced packaging offers a way to greatly improve performance and reduce power, but it also makes it harder to inspect these devices for real and latent defects. Higher density can lead to scattering of light, and heterogeneous integration in a package means it’s not always possible to see through all materials equally. Chris Rand, product line ma... » read more

Mission-Critical Devices Drive System-Level Test Expansion
By Laura Peters - 11 Jul, 2023 - Comments: 0

System-level testing is becoming essential for testing complex and increasingly heterogeneous chips, driven by rising demand for reliable parts in safety- and mission-critical applications. More and more chip manufacturers are jumping on the SLT bandwagon for high-volume manufacturing (HVM) of these devices. Unlike ATE and packaged device testing, SLT mimics actual semiconductor system opera... » read more

More Manufacturing Issues, More Testing
By Ed Sperling - 08 Feb, 2022 - Comments: 0

Douglas Lefever, CEO of Advantest America, sat down with Semiconductor Engineering to talk about changes in test, the impact of advanced packaging, and business changes that are happening across the flow. What follows are excerpts of that discussion. SE: What are the big changes ahead in test? Lefever: It's less about inflection points and more like moving from algebra to calculus in the ... » read more

Piecing Together Chiplets
By Mark LaPedus - 22 Jul, 2021 - Comments: 3

Several companies are implementing the chiplet model as a means to develop next-generation 3D-like chip designs, but this methodology still has a long way to go before it becomes mainstream for the rest of the industry. It takes several pieces to bring up a 3D chip design using the chiplet model. A few large players have the pieces, though most are proprietary. Others are missing some key co... » read more

Reliability Over Time And Space
By Ed Sperling - 13 Oct, 2020 - Comments: 0

The demand for known good die is well understood as multi-chip packages are used in safety-critical and mission-critical applications, but that alone isn't sufficient. As chips are swapped in and out of packages to customize them for specific applications, it will be the entire module that needs to be verified, simulated and tested, and analyzed. This is more complicated than it sounds for s... » read more

Problems And Solutions In Analog Design
By Ann Mutschler - 05 Aug, 2020 - Comments: 1

Advanced chip design is becoming a great equalizer for analog and digital at each new node. Analog IP has more digital circuitry, and digital designs are more susceptible to kinds of noise and signal disruption that have plagued analog designs for years. This is making the design, test and packaging of SoCs much more complicated. Analog components cause the most chip production test failures... » read more

The Race To Much More Advanced Packaging
By Mark LaPedus - 23 Jul, 2020 - Comments: 2

Momentum is building for copper hybrid bonding, a technology that could pave the way toward next-generation 2.5D and 3D packages. Foundries, equipment vendors, R&D organizations and others are developing copper hybrid bonding, which is a process that stacks and bonds dies using copper-to-copper interconnects in advanced packages. Still in R&D, hybrid bonding for packaging provides mo... » read more

Advanced Packaging Makes Testing More Complex
By Bryon Moyer - 07 Jul, 2020 - Comments: 1

The limits of monolithic integration, together with advances in chip interconnect and packaging technologies, have spurred the growth of heterogeneous advanced packaging where multiple dies are co-packaged using 2.5D and 3D approaches. But this also raises complex test challenges, which are driving new standards and approaches to advanced-package testing. While many of the showstopper issues... » read more

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