tag: Lam Research

Analysis Of BEOL Metal Schemes By Process Modeling
By Daebin Yim - 16 Nov, 2023 - Comments: 0

The semiconductor industry has been diligently searching for alternative metal line materials to replace the conventional copper dual damascene scheme, because as interconnect dimensions shrink, the barrier accounts for an increasing fraction of the total line volume. The barrier layer's dimensions cannot be scaled down as quickly as the metal line width (figure 1). Popular barrier materials su... » read more

Blog Review: November 15
By Jesse Allen - 15 Nov, 2023 - Comments: 0

Cadence's Neelabh Singh explores the process of lane initialization and link training in bringing up a high-speed link in USB4. Synopsys' Shela Aboud argues that TCAD should be an integral part of an EDA flow as it enhances design technology co-optimization with a way to experiment and determine what works and what doesn’t work at different process nodes using physics-based models. Siem... » read more

Gearing Up For Hybrid Bonding
By Laura Peters - 23 Oct, 2023 - Comments: 2

Hybrid bonding is becoming the preferred approach to making heterogeneous integration work, as the semiconductor industry shifts its focus from 2D scaling to 3D scaling. By stacking chiplets vertically in direct wafer-to-wafer bonds, chipmakers can leapfrog attainable interconnection pitch from 35µm in copper micro-bumps to 10µm or less. That reduces signal delay to negligible levels and e... » read more

The Impact Of Channel Hole Profiles On Advanced 3D NAND Structures
By Qingpeng Wang - 19 Oct, 2023 - Comments: 0

In a two-tier 3D NAND structure, the upper and lower channel hole profile can be different, and this combination of different profiles leads to different top-down visible areas. The visible area is the key metric to determine whether the bottom SONO layer can be punched through and ensure that the bit cells connect to the common source line. Performing channel hole profile splits on a silicon w... » read more

Chip Industry Talent Shortage Drives Academic Partnerships
By Liz Allan - 16 Oct, 2023 - Comments: 0

Universities around the world are forming partnerships with semiconductor companies and governments to help fill open and future positions, to keep curricula current and relevant, and to update and expand skills for working engineers. Talent shortages repeatedly have been cited as the number one challenge for the chip industry. Behind those concerns are several key drivers, and many more dom... » read more

Chip Industry Week In Review
By The SE Staff - 29 Sep, 2023 - Comments: 0

By Susan Rambo, Liz Allan, and Gregory Haley. TSMC rolled out the second version of its 3Dblox, which creates an infrastructure for stacking chiplets and other necessary components in a package, along with a standardized way of achieving that. Two novel features are chiplet mirroring for design reuse, and what is basically sandbox for power and thermal analysis of different design elements. ... » read more

When And Where To Implement AI/ML In Fabs
By Anne Meixner - 21 Sep, 2023 - Comments: 0

Deciphering complex interactions between variables is where machine learning and deep learning shine, but figuring out exactly how ML-based systems will be most useful is the job of engineers. The challenge is in pairing their domain expertise with available ML tools to maximize the value of both. This depends on sufficient quantities of good data, highly optimized algorithms, and proper tra... » read more

Securing Chip Manufacturing Against Growing Cyber Threats
By Anne Meixner - 17 Aug, 2023 - Comments: 0

Semiconductor manufacturers are wrestling with how to secure a highly specialized and diverse global supply chain, particularly as the value of their IP and their dependence upon software increases — along with the sophistication and resources of the attackers. Where methodologies and standards do exist for security, they often are confusing, cumbersome, and incomplete. There are plenty of... » read more

Chip Industry’s Technical Paper Roundup: August 1
By Liz Allan - 01 Aug, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=39 /] More Reading Technical Paper Library home » read more

Demonstrating The Capabilities Of Virtual Wafer Process Modeling And Virtual Metrology
By Technical Paper Link - 27 Jul, 2023 - Comments: 0

A technical paper titled “Review of virtual wafer process modeling and metrology for advanced technology development” was published by researchers at Coventor Inc., Lam Research. Abstract: "Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the p... » read more

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