Understanding CFETs, A Next Generation Transistor Architecture


Computing power has experienced exponential growth over the last 70 years. This has largely been achieved through transistor scaling. Due to a continuous reduction in the size of transistors, engineers have been able to pack more and more of them onto a single chip [1]. This has led to faster, more powerful, and more energy-efficient devices. Improvements in fabrication processes and materials,... » read more

Reducing Risk In The Semiconductor Supply Chain


Companies that were hit with chip shortages during the pandemic are changing their strategies to prevent future problems, deploying a combination of supply chain mapping, second sourcing, and digital transformation. Those shortages caused a $200 billion loss for automotive manufacturers, and the disruptions were far more widespread, in many cases lasting for years. Companies of all sorts wer... » read more

Sparking Climate Action With Earth Month Lightning Talks


In the age of rapidly advancing technology and global connectivity, it’s essential to recognize the impact of our actions on the planet. As industries evolve, so must our commitment to sustainability and environmental stewardship. In this spirit, the Climate Equity and Social Impact (CESI) working group, part of the SEMI Sustainability Initiative, last month hosted the semiconductor industry... » read more

Blog Review: May 15


Cadence's Anika Sunda suggests that RISC-V has opened numerous doors for innovation and believes EDA tools can help bridge the knowledge gap and foster a growing community of RISC-V developers. Synopsys' Alessandra Costa chats with industry experts about challenges facing analog design, what's needed for multi-die designs, and the potential of AI. Siemens' Bill Ji explains why understandi... » read more

Using Predictive Maintenance To Boost IC Manufacturing Efficiency


Predicting exactly how and when a process tool is going to fail is a complex task, but it's getting a tad easier with the rollout of smart sensors, standard interfaces, and advanced data analytics. The potential benefits of predictive maintenance are enormous. Higher tool uptime correlates with greater fab efficiency and lower operating costs, so engineers are pursuing multiple routes to boo... » read more

Chip Industry Week In Review


Synopsys refocused its security priorities around chips, striking a deal to sell off its Software Integrity Group subsidiary to private equity firms Clearlake Capital Group and Francisco Partners for about $2.1 billion. That deal comes on the heels of Synopsys' recent acquisition of Intrinsic ID, which develops physical unclonable function IP. Sassine Ghazi, Synopsys' president and CEO, said in... » read more

Predicting And Preventing Process Drift


Increasingly tight tolerances and rigorous demands for quality are forcing chipmakers and equipment manufacturers to ferret out minor process variances, which can create significant anomalies in device behavior and render a device non-functional. In the past, many of these variances were ignored. But for a growing number of applications, that's no longer possible. Even minor fluctuations in ... » read more

Enabling Advanced Devices With Atomic Layer Processes


Atomic layer deposition (ALD) used to be considered too slow to be of practical use in semiconductor manufacturing, but it has emerged as a critical tool for both transistor and interconnect fabrication at the most advanced nodes. ALD can be speeded up somewhat, but the real shift is the rising value of precise composition and thickness control at the most advanced nodes, which makes the ext... » read more

Exploring Process Scenarios To Improve DRAM Device Performance


In the world of advanced semiconductor fabrication, creating precise device profiles (edge shapes) is an important step in achieving targeted on-chip electrical performance. For example, saddle fin profiles in a DRAM memory device must be precisely fabricated during process development in order to avoid memory performance issues. Saddle fins were introduced in DRAM devices to increase channel l... » read more

Review Of Virtual Wafer Process Modeling And Metrology For Advanced Technology Development


Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the process flow and ultimately quantifying its physical and electrical properties are critical steps in yielding mature technology. The standard build, test, and wait model of technology development ... » read more

← Older posts Newer posts →