Is EUV Making Progress?

By Ann Mutschler - 18 Jun, 2015 - Comments: 4

By Ann Steffora Mutschler & Ed Sperling EUV has been promised for a couple of decades, counted on for at least three process nodes on the ITRS roadmap, and considered essential to chip manufacturing since 22nm. Billions of dollars have been invested in R&D, engineering teams from around the world have contributed to its development, and still serious problems persist. Just how close... » read more

Semiconductor R&D Crisis?

By Mark LaPedus - 11 Jun, 2015 - Comments: 3

Research and development is a sometimes forgotten but critical element in the semiconductor industry. The delicate R&D ecosystem enables many of the key breakthroughs in the business. But there could be a troubling trend, if not a crisis, brewing on two fronts in the R&D arena. On one front, R&D costs for semiconductor technologies are escalating at each node. Higher R&D costs are not only ... » read more

Blog Review: May 27

By Jesse Allen - 27 May, 2015 - Comments: 0

With the launch of UNICEF and ARM's 'Wearables for Good' design challenge, David Maidment digs into the program's details and how unobtrusive wearables and sensor technology benefits not only consumers in affluent countries, but could improve conditions for those in the developing world as well. From an ultracompact beamsplitter that could boost processing power for supercomputers within the... » read more

10nm Fab Challenges

By Mark LaPedus - 21 May, 2015 - Comments: 1

After a promising start in 2015, the semiconductor equipment industry is currently experiencing a slight lull. The pause is expected to be short-lived, however. Suppliers of [getkc id="208" comment="3D NAND"] devices are expected to add more fab capacity later this year. And about the same time, foundries are expected to order the first wave of high-volume production tools for 10nm. At 10nm... » read more

The Roadmap To 5nm

By SEMI - 11 May, 2015 - Comments: 0

By Debra Vogler Among the challenges the semiconductor industry will be facing as it moves down the path to node 5 are resistance-capacitance (RC) management and integration. SEMI is pleased to announce a SEMICON West 2015 STS technical program exploring these and other high-volume manufacturing challenges. According to An Steegen, SVP of Process Technology at imec, the list of RC managemen... » read more

Next EUV Challenge: Mask Inspection

By Mark LaPedus - 16 Apr, 2015 - Comments: 2

Extreme ultraviolet ([gettech id="31045" comment="EUV"]) lithography is still not ready for prime time, but the technology finally is moving in the right direction. The EUV light source, for example, is making progress after years of delays and setbacks. Now, amid a possible breakthrough in EUV, the industry is revisiting a nagging issue and asking a simple question: How do you inspect EUV p... » read more

Flash Dance For Inspection And Metrology

By Mark LaPedus - 16 Apr, 2015 - Comments: 0

Chipmakers are moving from planar technology to an assortment of 3D-like architectures, such as 3D NAND and finFETs For these devices, chipmakers face a multitude of challenges in the fab. But one surprising and oft-forgotten technology is emerging as perhaps the biggest challenge in both logic and memory—process control. Process control includes metrology and wafer inspection. Metrolo... » read more

Searching For 3D Metrology

By Mark LaPedus - 19 Mar, 2015 - Comments: 3

In the previous decade, chipmakers made a bold but necessary decision to select the [getkc id="185" kc_name="finFET"] as the next transistor architecture for the IC industry. Over time, though, chipmakers discovered that the finFET would present some challenges in the fab. Deposition, etch and lithography were the obvious hurdles, but chipmakers also saw a big gap in metrology. In fact,... » read more

Issues And Options At 5nm

By Mark LaPedus - 19 Mar, 2015 - Comments: 0

While the foundries are ramping up their processes for the 16nm/14nm node, vendors are also busy developing technologies for 10nm and beyond. In fact, chipmakers are finalizing their 10nm process offerings, but they are still weighing the technology options for 7nm. And if that isn’t enough, IC makers are beginning to look at the options at 5nm and beyond. Today, chipmakers can see a p... » read more

Blog Review: March 18

By Jesse Allen - 18 Mar, 2015 - Comments: 0

How do you quantify effort spent in FPGA verification? Mentor's Harry Foster tackles the question in his latest installment of the Wilson Research Group functional verification study. A new frontier of design challenges is rapidly emerging, according to ARM CEO Simon Segars. Cadence's Brian Fuller brings us his keynote address at CDNLive. Synopsys' Tushar Mattu is back with more on AXI VI... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?