Single Vs. Multi-Patterning EUV

By Mark LaPedus - 25 Mar, 2019 - Comments: 5

Extreme ultraviolet (EUV) lithography finally is moving into production, but foundry customers now must decide whether to implement their designs using EUV-based single patterning at 7nm, or whether to wait and instead deploy EUV multiple patterning at 5nm. Each patterning scheme has unique challenges, making that decision more difficult than it might appear. Targeted for 7nm, single pattern... » read more

Battling Fab Cycle Times

By Mark LaPedus - 16 Feb, 2017 - Comments: 9

The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node. Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and... » read more

Why EUV Is So Difficult

By Mark LaPedus - 17 Nov, 2016 - Comments: 23

For years, extreme ultraviolet (EUV) lithography has been a promising technology that was supposed to help enable advanced chip scaling. But after years of R&D, EUV is still not in production despite major backing from the industry, vast resources and billions of dollars in funding. More recently, though, [gettech id="31045" comment="EUV"] lithography appears to be inching closer to pos... » read more

Multiple Lithography Options Still Remain in Play

By Paula Doe - 03 Aug, 2015 - Comments: 1

The throughput and uptime of EUV, and the overlay accuracy of 193nm immersion lithography, continue to steadily improve, though neither is yet ready for 10nm production, according to speakers at SEMICON West. Mike Lercel, ASML director, Product Marketing, reported several EUV tool sites achieved 70 percent uptime for more than a week, and one customer site had done so for more than four ... » read more

10nm Fab Challenges

By Mark LaPedus - 21 May, 2015 - Comments: 1

After a promising start in 2015, the semiconductor equipment industry is currently experiencing a slight lull. The pause is expected to be short-lived, however. Suppliers of [getkc id="208" comment="3D NAND"] devices are expected to add more fab capacity later this year. And about the same time, foundries are expected to order the first wave of high-volume production tools for 10nm. At 10nm... » read more

The Bumpy Road To 10nm FinFETs

By Mark LaPedus - 21 May, 2015 - Comments: 0

Foundry vendors are currently ramping up their 16nm/14nm [getkc id="185" kc_name="finFET"] processes in the market. Vendors are battling each other for business in the arena, although the migration from planar to finFETs is expected to be a slow and expensive process. Still, despite the challenges at 16nm/14nm, vendors are gearing up for the next battle in the foundry business—the 10nm nod... » read more

First Look: 10nm

By Ed Sperling - 29 Jan, 2015 - Comments: 6

As the semiconductor industry begins grappling with mass production at 14/16nm process nodes, work is already underway at 10nm. Tools are qualified, IP is characterized, and the first test chips are being produced. It's still too early for production, of course—perhaps three years too early—but there is enough information being collected to draw at least some impressions about just how toug... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer