The Next Phase Of Machine Learning


Machine learning is all about doing complex calculations on huge volumes of data with increasing efficiency, and with a growing stockpile of success stories it has rapidly evolved from a rather obscure computer science concept into the go-to method for everything from facial recognition technology to autonomous cars. [getkc id="305" kc_name="Machine learning"] can apply to every corporate fu... » read more

ARC HS4x And HS4xD CPUs


Synopsys’ DesignWare ARC CPUs comprise a family of highly configurable and customizable processor cores, which ship in nearly two billion chips per year. ARC’s popularity in embedded devices makes the company second only to ARM in the number of chips that integrate its licensable CPUs. More than 230 ARC licensees use the cores in products that span a broad range of embedded applications, su... » read more

Where Are The IoT Industry Standards?


Are you ready for some Internet of Things standards? Good, because you can help make them. The IoT is proceeding apace as a business, eagerly embraced by such corporate behemoths as Cisco Systems, General Electric, IBM, and Verizon Communications. What’s lacking is the codification of industry standards for the IoT, as many companies have aligned with groups that have competing agendas and... » read more

The Week In Review: IoT


Analysis After reading a blog post touting the Internet of Things for home security, Jon Hedren wrote this post detailing how IoT-based home systems can be easily compromised and could fail in multiple ways. “The IoT ‘dream’ as sold by the industry is pretty cool, but it’s still just a dream. For now, these devices remain generally shoddy, insecure, and easily breakable—and must be t... » read more

Easing Heterogeneous Cache Coherent SoC Design Using Arteris’ Ncore Interconnect IP


Heterogeneous processing has become a hallmark of mobile SoCs, but designing cache coherency across these diverse processing elements can be difficult. Standard on-chip interfaces and network-on-a-chip (NoC) technology are the first step, giving architects IP to efficiently connect compute processing elements as different as CPUs, GPUs, and DSPs. Hardware IP to enable coherent communication bet... » read more

Security In 2.5D


The long-anticipated move to 2.5D and fan-outs is raising some familiar questions about security. Will multiple chips combined in an advanced package be as secure as SoCs where everything is integrated on the same die? The answer isn't a simple yes or no. Put in perspective, all chips are vulnerable to [getkc id="253" kc_name="side channel attacks"], hacking of memory—a risk that increases... » read more

CEVA Targets Wearables


Coinciding with the announcement of an integrated platform based on a single TeakLite-4 DSP, handling Audio/Voice, Sensor Fusion, always-on UI and Connectivity- Linley Group Mobile Chip Report, By Linley Gwennap (May 5, 2014) describes how CEVA’s new and ground breaking platform is a starter kit of hardware and software blocks that a company can use to build a processor for its wearable produ... » read more

Synopsys ARC HS Processors: High-Speed Licensable CPU Cores for Embedded Applications


Synopsys is a leading EDA company with an extensive portfolio of licensable DesignWare intellectual property (IP). The portfolio includes interface IP, analog IP, embedded memories, and logic libraries. Although most chip designers know that DesignWare IP also includes licensable CPU cores and subsystems, many are surprised to learn that Synopsys is second only to ARM in the number of chips tha... » read more

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