tag: linting

Easing The Burden Of Early Bug Detection
By Rob van Blommestein - 26 Aug, 2021 - Comments: 0

Integrated circuit designers are under constant pressure to deliver bug free code that meets ever more rigorous requirements. It is well known that the more bugs that can be detected early in the development process, the faster and easier that development effort will be. However, early bug detection requires a verification overhead on the designer that can be onerous and impact the design proce... » read more

Better Security, Lower Cost
By Ed Sperling - 10 Aug, 2020 - Comments: 0

For years, chipmakers have marginalized security in chips, relying instead on software solutions. Eventually that approach caught up with them, creating near panic in a scramble to plug weaknesses involving speculative execution and branch prediction, as well as the ability to read the data from chips with commercially available tools such as optical probes. There were several reasons for th... » read more

Linting RISC-V Designs
By Alex Gnusin - 30 Jul, 2020 - Comments: 0

As the open-source RISC-V instruction set architecture (ISA) continues to gain momentum, the growing number of RISC-V design solutions and their flexibility creates a problem when choosing the most reliable and robust solution from a number of contenders. Sure, a RISC-V IP design must be compliant to basic ISA standards and should contain a testing suite demonstrating that compliance. But sh... » read more

Linting With ALINT-PRO Within Active-HDL
By Aldec - 24 Oct, 2018 - Comments: 0

Active-HDL suggests an early-bug-detection flow via the integration with ALINT-PRO. The Active-HDL user has an access to both different linting methodologies supported by ALINT-PRO: full chip-level linting and unit linting. Both methods complement each other and are usually applied at different stages of the design cycle. Unit linting is a relatively new approach that is well combinable with... » read more

UPF-Aware Clock-Domain Crossing
By Ed Sperling - 29 Aug, 2018 - Comments: 0

Synopsys’ Namit Gupta talks with Semiconductor Engineering about low-power design techniques at the most advanced process nodes, including how to verify the impact of CDC on power at the register transfer level, how to avoid bugs caused by the post-RTL insertion of low-power devices such as isolation, retention and level shifters. https://youtu.be/HwRe9DHLfmg » read more

Achieving RTL-To-Netlist Equivalence
By Aldec - 30 Jan, 2018 - Comments: 0

Running quality tests and regression at RTL level, and even fixing all discovered design bugs does not guarantee the flawless hardware design. To make sure there are no bugs in the target hardware, there is a need to ensure flawless transformation of RTL code to the technology-dependent netlist. This in turns sets the requirements for the “design-for-implementation” coding, where designers ... » read more

Choosing The Right Superlinting Technology For Early RTL Code Signoff
By Cadence - 28 Jun, 2017 - Comments: 0

No one can afford to go through weeks of verification only to discover problems in the register- transfer level (RTL) code that might not be functionally wrong, but do not follow established rules for successful implementation. Traditional lint tools have become ineffective in evaluating RTL code for today’s larger, more complex designs. However, superlinting technology, such as the Cadence J... » read more

Sigasi: Cleaner VHDL And SystemVerilog
By Ed Sperling - 30 Jan, 2017 - Comments: 0

Hardware engineers always have looked at software tools and methodologies with a certain degree of envy. While the hardware side has embraced the discipline necessary to get products right prior to release, in large part because it's too expensive to fix an error in hardware, the tools and languages are generally clunkier and the methodologies are much more rigid. Like software, they have to in... » read more

Taming Lint With Formal
By Ravindra Aneja - 09 Apr, 2015 - Comments: 1

Designers have been using Linting tools for many years to ensure designs adhere to recommended coding guidelines. Linting tools verify that RTL is written in an unambiguous way to ensure that downstream tools (simulation, synthesis, etc.) do not interpret the code incorrectly, resulting in design, verification, timing or implementation issues. Linting tools take advantage of fast and shallow... » read more

Does SoC Signoff Mean More Than RTL?
By Graham Bell - 30 May, 2013 - Comments: 0

As the cost of failure continues to rise, SoC engineers see the growing importance of ensuring their work is as correct as possible as soon as possible in the design process. They cannot afford to carry errors forward from one stage to the next, where their impact grows while their causes become more obscured. This requirement is driving the shift in design exploration and handoff to the reg... » read more

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