The High NA EUV Imperative: How Computational Lithography Solutions Enable Us To Think Smaller

By Gandharv Bhatara - 21 Mar, 2024 - Comments: 0

The future of computing depends on miniaturization, and extreme ultraviolet lithography (EUV) is one key enabler. Until recently, we have relied on low numerical aperture (NA) EUV systems with an aperture of 0.33 to help us reduce the size of integrated circuits (ICs). As with deep ultraviolet (DUV) technology, this has begun to reach its limits. High NA EUV lithography with a 0.55 aperture rep... » read more

Industry Luminaries Highlight Opportunities For Advancing The Non-EUV Leading Edge

By Jan Willis - 19 Dec, 2023 - Comments: 0

The eBeam Initiative’s 12th annual Luminaries survey in 2023 reported a range of nodes from >5nm to 14nm as the most advanced non-EUV nodes using 193i lithography. A panel of semiconductor photomask and lithography experts debated several of the survey results, including this one, to provide more insights behind the results. Aki Fujimura, CEO of D2S, Inc., the managing company sponsor of t... » read more

Semiconductor Device Manufacturing Process Challenges And Opportunities

By Andreas Bier - 07 Dec, 2023 - Comments: 0

Semiconductor device manufacturing involves a complex series of processes that transform raw materials into finished devices. The process typically involves four major stages: wafer fabrication, wafer testing, assembly or packaging, and final testing. Each stage has its own unique set of challenges and opportunities. The semiconductor device manufacturing process faces several challenges, inclu... » read more

Curvilinear Mask Patterning For Maximizing Lithography Entitlement

By Synopsys - 15 Nov, 2023 - Comments: 0

Curvilinear Mask Patterning is a cutting-edge lithography technique that promises to maximize lithography entitlement by addressing complex design challenges and critical yield limiters. However, its widespread deployment has been limited by significant computational challenges. This paper includes practical solutions to overcome the computational challenges associated with this technique, as w... » read more

Research Bits: September 19

By Jesse Allen - 19 Sep, 2023 - Comments: 0

Measuring lithography plasma sources Researchers from the University of Twente developed a tool that can measure the size of a plasma source and the color of the light it emits simultaneously, which they say could be used to improve lithography machines. “Traditionally, we could only look at the amount of light produced, but to further improve the chipmaking process, we also want to study... » read more

The Glass Substrate Question: When Will It Replace Copper Clad Laminate?

By Keith Best - 12 Sep, 2023 - Comments: 0

"When will glass replace copper clad laminate on advanced IC substrates?" That’s a question many on the heterogeneous integration (HI) side of the semiconductor industry are asking. Unfortunately, the answer is not straightforward. But before we get to answering that, let’s take an advanced IC substrate (AICS) refresher. In other words, how did we get to the point where glass substrat... » read more

High-NA EUV Progress And Problems

By Gregory Haley - 22 Aug, 2023 - Comments: 0

High-NA EUV will enable logic scaling for at least the next couple process nodes. It’s complex, expensive, and a feat of optical engineering, but there are a lot of components with mixed progress. Harry Levinson, principal lithographer at HJL Lithography, talks about when this technology will likely show up, what problems still need to be resolved, and what comes next. Related Readin... » read more

Is Maskless Lithography Coming Into Its Own?

By Katherine Derbyshire - 17 Aug, 2023 - Comments: 0

Lithographers have always faced tradeoffs between speed and flexibility. Steppers are very good at printing hundreds or thousands of identical features onto hundreds or thousands of wafers. They are not especially good at handling surfaces with significant topography, though. Nor is customization feasible. Every exposure uses the same reticle. Direct write e-beam lithography has long been us... » read more

Direct Synthesis of Planar (2D) Micro and Nanopatterned Epitaxial Graphene on SiC

By Technical Paper Link - 28 Jul, 2023 - Comments: 0

A technical paper titled “Direct synthesis of nanopatterned epitaxial graphene on silicon carbide” was published by researchers at University of Technology Sydney, Ludwig-Maxilimians Universität München, Monash University, and Imperial College London. Abstract: "This article introduces a straightforward approach for the direct synthesis of transfer-free, nanopatterned epitaxial graphene... » read more

High-NA Lithography Starting To Take Shape

By Gregory Haley - 25 Jul, 2023 - Comments: 3

The future of semiconductor technology is often viewed through the lenses of photolithography equipment, which continues to offer better resolution for future process nodes despite an almost perpetual barrage of highly challenging technological issues. For years, lithography was viewed as the primary manufacturing-related gating factor to continued device scaling, beset by multiple delays th... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?