Analysis Of Pattern Distortion By Panel Deformation And Addressing It By Using Extremely Large Exposure Field Fine-Resolution Lithography


The growing demand for heterogeneous integration is driven by the 5G market. This includes smartphones, data centers, servers, high-performance computing (HPC), artificial intelligence (AI) and internet of things (IoT) applications. Next-generation packaging technologies require tighter overlay to accommodate larger package sizes with fine-pitch chip interconnects on large-format flexible panel... » read more

How To Compare Chips


Traditional metrics for semiconductors are becoming much less meaningful in the most advanced designs. The number of transistors packed into a square centimeter only matters if they can be utilized, and performance per watt is irrelevant if sufficient power cannot be delivered to all of the transistors. The consensus across the chip industry is that the cost per transistor is rising at each ... » read more

The High Price Of Smaller Features


The semiconductor industry’s push for higher numerical apertures is driven by the relationship between NA and critical dimension. As the NA goes up, the CD goes down: Where λ is the wavelength and k1 is a process coefficient. While 0.55 NA exposure systems will improve resolution, Larry Melvin, principal engineer at Synopsys, noted that smaller features always come with a process cos... » read more

For The Love Of Theatre And Mask-Making


Naoya Hayashi has been a friend and important contributor to the eBeam Initiative from our start over 13 years ago. We’re just one of the many interests he has embraced and championed over his 45 year career at DNP. Now it’s our turn to embrace him and thank him for the wonderful memories as he pursues his next chapter after retiring as the first research fellow from DNP this June. Aki Fuji... » read more

High-NA EUV May Be Closer Than It Appears


High-NA EUV is on track to enable scaling down to the Angstrom level, setting the stage for chips with even higher transistor counts and a whole new wave of tools, materials, and system architectures. At the recent SPIE Advanced Lithography conference, Mark Phillips, director of lithography hardware and solutions at Intel, reiterated the company’s intention to deploy the technology in high... » read more

Shortages Spark Novel Component Lifecycle Solutions


The semiconductor industry’s supply chain problems are prompting some innovative solutions and workarounds, and while they don't solve all problems, they are improving efficiency and extending equipment lifetimes. The shortages, which affect everything from the chips used in automotive, IoT, and consumer ICs to the equipment used to manufacture and test them — span global supply lines. T... » read more

ASD process that was performed in situ on the etch chamber


New research paper entitled "Plasma-based area selective deposition for extreme ultraviolet resist defectivity reduction and process window improvement" from TEL Technology Center, Americas and IBM Research. Abstract: "Extreme ultraviolet (EUV) lithography has overcome significant challenges to become an essential enabler to the logic scaling roadmap. However, it remains limited by stocha... » read more

Review of essential use of fluorochemicals in lithographic patterning and semiconductor processing


New academic paper by researchers from Cornell University.   Abstract "We identify and describe categories of fluorochemicals used to produce advanced semiconductors within the lithographic patterning manufacturing processes. Topics discussed include the per- and polyfluoroalkyl substance (PFAS) materials used and their necessary attributes for successful semiconductor manufacturing... » read more

Unsolved Issues In Next-Gen Photomasks


Experts at the Table: Semiconductor Engineering sat down to discuss optical and EUV photomasks issues, as well as the challenges facing the mask business, with Naoya Hayashi, research fellow at DNP; Peter Buck, director of MPC & mask defect management at Siemens Digital Industries Software; Bryan Kasprowicz, senior director of technical strategy at Hoya; and Aki Fujimura, CEO of D2S. What f... » read more

Photomask Challenges At 3nm And Beyond


Experts at the Table: Semiconductor Engineering sat down to discuss optical and EUV photomasks issues, as well as the challenges facing the mask business, with Naoya Hayashi, research fellow at DNP; Peter Buck, director of MPC & mask defect management at Siemens Digital Industries Software; Bryan Kasprowicz, senior director of technical strategy at Hoya; and Aki Fujimura, CEO of D2S. What f... » read more

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