tag: low-power design

Hardware-Software Co-Design Reappears
By Brian Bailey - 25 Jul, 2019 - Comments: 1

The core concepts in hardware-software co-design are getting another look, nearly two decades after this approach was first introduced and failed to catch on. What's different this time around is the growing complexity and an emphasis on architectural improvements, as well as device scaling, particularly for AI/ML applications. Software is a critical component, and the more tightly integrate... » read more

Power Is Limiting Machine Learning Deployments
By Brian Bailey - 25 Jul, 2019 - Comments: 3

The total amount of power consumed for machine learning tasks is staggering. Until a few years ago we did not have computers powerful enough to run many of the algorithms, but the repurposing of the GPU gave the industry the horsepower that it needed. The problem is that the GPU is not well suited to the task, and most of the power consumed is waste. While machine learning has provided many ... » read more

Accurate Power Analysis Using Real Software Workloads
By Johannes Stahl - 16 Jul, 2019 - Comments: 0

Over the last decade or so, power consumption has become a major issue in the design of many types of electronic products. Of course, power has always mattered for battery-operated devices, but the complexity of portable electronics and the size of the chips they contain have grown significantly. For plugged-in devices, from desktop computers to server racks in a data center, power plays a majo... » read more

Low-Power Design Becomes Even More Complex
By Ann Mutschler - 16 Jul, 2019 - Comments: 0

Throughout the SoC design flow, there has been a tremendous amount of research done to ease the pain of managing a long list of power-related issues. And while headway has been made, the addition of new application areas such as AI/ML/DL, automotive and IoT has raised as many new problems as have been solved. The challenges are particularly acute at leading-edge nodes where devices are power... » read more

The Power Of Integrating Bluetooth Low Energy Into SoCs
By Synopsys - 15 Jul, 2019 - Comments: 0

The Bluetooth Low Energy (BLE) specification, released in 2011, enables designers of System-on-Chips (SoCs) to maximize the battery life of IoT devices and minimize the implementation costs of wireless sensors and other “connected things” by maximizing sleep time and simplifying Radio operation. Because it is built on the established ecosystem of Bluetooth Classic for mobile phones and P... » read more

Effective Elements List And Transitive Natures Of UPF Commands
By Mentor, a Siemens Business - 15 Jul, 2019 - Comments: 0

Although UPF is very well defined through IEEE 1801 LRM, it is often difficult to comprehend many primitive and inherent features of individual UPF commands-options or relations between different varieties of UPF commands-options. In this paper, we provide a simplistic approach to find inherent links between UPF commands-options through their transitive nature. We also explain how these inheren... » read more

Differential Energy Analysis To Optimize Mobile GPU Power
By Ansys - 15 Jul, 2019 - Comments: 0

Operating power has become one of the most important metrics for modern electronic devices. Qualcomm Technologies, a world-class mobile solution provider, significantly reduced power consumption in an already challenging market by performing power analysis at RTL using ANSYS PowerArtist. Qualcomm Technologies was able to reduce dynamic power by 10 percent through this approach. To read more,... » read more

How To Improve ML Power/Performance
By Ed Sperling - 12 Jul, 2019 - Comments: 0

Raymond Nijssen, vice president and chief technologist at Achronix, talks about the shift from brute-force performance to more power efficiency in machine learning processing, the new focus on enough memory bandwidth to keep MAC functions busy, and how dynamic range, precision and locality can be modified to improve speed and reduce power. » read more

Sidestepping Moore’s Law
By Mark LaPedus - 20 Jun, 2019 - Comments: 2

Calvin Cheung, vice president of engineering at ASE, sat down with Semiconductor Engineering to talk about advanced packaging, the challenges involved with the technology, and the implications for Moore’s Law. What follows are excerpts of that conversation. SE: What are some of the big issues with IC packaging today? Cheung: Moore’s Law is slowing down, but transistor scaling will co... » read more

Week In Review: Design, Low Power
By Jesse Allen - 14 Jun, 2019 - Comments: 0

M&A Intel will acquire Barefoot Networks, a maker of programmable Ethernet switch silicon and the P4 networking programming language for data centers. Founded in 2013, the Santa Clara-based company has raised $155.4 million in funding. Terms of the deal were not disclosed, but Intel expects the acquisition to be final in the third quarter of this year. Tools & IP Mentor extended it... » read more

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