tag: low-power design

Moore’s Law Now Requires Advanced Packaging
By Ed Sperling - 18 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; and Tien Shiah, senior manager for memory at Samsung. W... » read more

Target: 50% Reduction In Memory Power
By Brian Bailey - 11 Apr, 2019 - Comments: 3

Memory consumes about 50% or more of the area and about 50% of the power of an SoC, and those percentages are likely to increase. The problem is that static random access memory (SRAM) has not scaled in accordance with Moore's Law, and that will not change. In addition, with many devices not chasing the latest node and with power becoming an increasing concern, the industry must find ways to... » read more

Optimization Challenges For Safety And Security
By Brian Bailey - 11 Apr, 2019 - Comments: 0

Complexity challenges long-held assumptions. In the past, the semiconductor industry thought it understood performance/area tradeoffs, but over time it became clear this is not so simple. Measuring performance is no longer an absolute. Power has many dimensions including peak, average, total energy and heat, and power and function are tied together. Design teams are now dealing with the impl... » read more

The Growing Challenge Of Thermal Guard-Banding
By Ann Mutschler - 18 Mar, 2019 - Comments: 1

Guard-banding for heat is becoming more difficult as chips are used across a variety of new and existing applications, forcing chipmakers to architect their way through increasingly complex interactions. Chips are designed to operate at certain temperatures, and it is common practice to develop designs with some margin to ensure correct functionality and performance throughout the operat... » read more

Power Budgets At 3nm And Beyond
By Ed Sperling - 14 Mar, 2019 - Comments: 0

There is high confidence that digital logic will continue to shrink at least to 3nm, and possibly down to 1.5nm. Each of those will require significant changes in how design teams approach power. This is somewhat evolutionary for most chipmakers. Five years ago there were fewer than a handful of power experts in most large organizations. Today, everyone deals with power in one way or another... » read more

Memory Tradeoffs Intensify in AI, Automotive Applications
By Ann Mutschler - 14 Mar, 2019 - Comments: 0

The push to do more processing at the edge is putting a strain on memory design, use models and configurations, leading to some complex tradeoffs in designs across a variety of markets. The problem is these architectures are evolving alongside these new markets, and it isn't always clear how data will move across these chips, between devices, and between systems. Chip architectures are becom... » read more

Designing An AI SoC
By Ed Sperling - 11 Mar, 2019 - Comments: 0

Susheel Tadikonda, vice president of networking and storage at Synopsys, looks at how to achieve economies of scale in AI chips and where the common elements are across all the different architectures. https://youtu.be/fm0kxnj3DuM » read more

Week In Review: Design, Low Power
By Jesse Allen - 01 Mar, 2019 - Comments: 0

Tools & IP OneSpin Solutions debuted the Hardware Metric Calculation (HMC) App, which uses automatically extracted design information to calculate key hardware metrics to comply with functional safety standards. In particular, it focuses on automotive and autonomous driving SoCs needing to meet the highest functional safety requirements defined by the ISO 26262 standard. The HMC App calcul... » read more

How To Reduce Thermal Guard-Banding
By Ramsay Allen - 14 Feb, 2019 - Comments: 0

Accuracy in temperature sensors can have a big impact in designs from 40nm down to 7nm and beyond, reducing the amount of guard-banding that is required, which in turn can lower the power and extend the life and reliability of components. But at these process geometries, not all sensors measure temperature equally. Thermal guard-banding is a very important consideration for design teams, and... » read more

Adapting Mobile To A Post-Moore’s Law Era
By Ann Mutschler - 14 Feb, 2019 - Comments: 0

The slowdown in Moore's Law is having a big impact on chips designed for the mobile market, where battery-powered devices need to still improve performance with lower power. This hasn't slowed down performance or power improvements, but it has forced chipmakers and systems companies to approach designs differently. And while feature shrinks will continue for the foreseeable future, they are ... » read more

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