tag: low-power design

The Next Big Leap: Energy Optimization
By Brian Bailey - 16 Nov, 2020 - Comments: 1

The relationship between power and energy is technically simple, but its implication on the EDA flow is enormous. There are no tools or flows today that allow you to analyze, implement, and optimize a design for energy consumption, and getting to that point will require a paradigm shift within the semiconductor industry. The industry talks a lot about power, and power may have become a more ... » read more

The Next Phase Of Computing
By Ed Sperling - 16 Nov, 2020 - Comments: 0

Apple's new M1 chip offers a glimpse of what's ahead, and not just from Apple. Being able to get 18 to 20 hours of battery life from a laptop computer moves the ball much farther down the field in semiconductor design. All of this is entirely dependent on the applications, of course. But what's important here is how much battery life and performance can be gained by designing hardware specif... » read more

Dealing With Sub-Threshold Variation
By Bryon Moyer - 12 Nov, 2020 - Comments: 0

Chipmakers are pushing into sub-threshold operation in an effort to prolong battery life and reduce energy costs, adding a whole new set of challenges for design teams. While process and environmental variation long have been concerns for advanced silicon process nodes, most designs operate in the standard “super-threshold” regime. Sub-threshold designs, in contrast, have unique variatio... » read more

Difficult Memory Choices In AI Systems
By Ann Mutschler - 12 Nov, 2020 - Comments: 0

The number of memory choices and architectures is exploding, driven by the rapid evolution in AI and machine learning chips being designed for a wide range of very different end markets and systems. Models for some of these systems can range in size from 10 billion to 100 billion parameters, and they can vary greatly from one chip or application to the next. Neural network training and infer... » read more

Faster Inferencing At The Edge
By Ed Sperling - 09 Nov, 2020 - Comments: 0

Cheng Wang, senior vice president of engineering at Flex Logix, talks about inferencing at the edge, what are some of the main considerations in designing and choosing an inferencing chip, why programmability and modularity are important, and how hardware-software co-design with algorithms can improve performance and power. » read more

Speeding Up AI With Vector Instructions
By Ann Mutschler - 04 Nov, 2020 - Comments: 0

A search is underway across the industry to find the best way to speed up machine learning applications, and optimizing hardware for vector instructions is gaining traction as a key element in that effort. Vector instructions are a class of instructions that enable parallel processing of data sets. An entire array of integers or floating point numbers is processed in a single operation, elim... » read more

Security Tradeoffs In Chips And AI Systems
By Ed Sperling - 03 Nov, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss the cost and effectiveness of security in chip architectures and AI systems with with Vic Kulkarni, vice president and chief strategist at Ansys; Jason Oberg, CTO and co-founder of Tortuga Logic; Pamela Norton, CEO and founder of Borsetta; Ron Perez, fellow and technical lead for security architecture at Intel; and Tim Whitfield, vice president of s... » read more

Performance and Power Tradeoffs At 7/5nm
By Ed Sperling - 27 Oct, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at Synopsys; Bryan Bowyer, director of engineering at Mentor, a Siemens Business; Kiran Burli, senior director of marketing for Arm's Physical Design Group; Kam Kittrell, senior product management group d... » read more

Increase In Analog Problems
By Brian Bailey - 19 Oct, 2020 - Comments: 6

Analog and mixed signal design has always been tough, but a resent survey suggests that the industry has seen significantly increased failures in the past year because the analog circuitry within an ASIC was out of tolerance. What is causing this spike in failures? Is it just a glitch in the data, or are these problems real? The answer is complicated, and to a large extent it depends heavily... » read more

Slower Metal Bogs Down SoC Performance
By Bryon Moyer - 15 Oct, 2020 - Comments: 0

Metal interconnect delays are rising, offsetting some of the gains from faster transistors at each successive process node. Older architectures were born in a time when compute time was the limiter. But with interconnects increasingly viewed as the limiter on advanced nodes, there’s an opportunity to rethink how we build systems-on-chips (SoCs). ”Interconnect delay is a fundamental tr... » read more

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