Tech Talk: Power Tools

By Ed Sperling - 27 May, 2015 - Comments: 0

At 200 million gates, using standard tools for power will add weeks to the semiconductor design process. Vijay Chobisa, product marketing manager at Mentor Graphics, talks with Semiconductor Engineering about where the problems are and how to solve them. [youtube vid=w7yEdtaIb9A] » read more

How Do We Push The Limits Of Power?

By Brian Fuller - 14 May, 2015 - Comments: 0

Just how far will we be able to push down power in electronics system design? A bit farther, according to experts presenting at the recent Electronic Design Processes Symposium in Monterey. A combination of materials, techniques, technology and cultural change will get the industry there. During a panel session comparing fully-depleted silicon-on-insulator (FD-SOI) with finFET technology, J... » read more

FD-SOI Vs. FinFETs

By Ed Sperling - 13 May, 2015 - Comments: 3

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

The Next Generation Of Wearables

By Ernest Worthman - 07 May, 2015 - Comments: 0

As the wearable market begins to take root, so has the focus on ultra-low power design—with some unique headaches that are unique to wearables. To begin with, there is much attention being paid to this market because of the almost staggering predictions associated with it. While numbers vary greatly, IDC predicts as many as 126 million units will be shipping annually by 2019. The five-year... » read more

FD-SOI Vs. FinFETs

By Ed Sperling - 30 Apr, 2015 - Comments: 0

FD-SOI Vs. FinFETs

By Ed Sperling - 16 Apr, 2015 - Comments: 1

Low Power Trends Toward FinFET

By Mary Ann White - 12 Feb, 2015 - Comments: 0

My previous blog, Power Reduction Techniques, covered which low power techniques were applicable for various process nodes, from larger planar CMOS process technologies through finFET. The 16 and 14nm finFET-based process nodes are moving into production this year, and we are seeing many companies rapidly move their designs to finFET. In my last post, I noted some of the reasons why finFET is s... » read more

One-On-One: Walid Abu-Hadba

By Ed Sperling - 11 Feb, 2015 - Comments: 0

Walid Abu-Hadba, chief product officer at [getentity id="22021" e_name="Ansys"] (and a former top executive at Microsoft), sat down with Semiconductor Engineering to talk about systems engineering and why the starting point is no longer the SoC. What follows are excerpts of that conversation. SE: How do you define system? Abu-Hadba: It's everything. It's the entire product and where the p... » read more

Redefining Progress

By Ed Sperling - 22 Jan, 2015 - Comments: 0

After lots of wrangling over the whether Moore's Law is alive, dead, or languishing at somewhere in between, that discussion now seems about as relevant as the look and feel of Apple's early Macintosh operating system—an issue that back in the 1980s spawned a very public war with Microsoft. Today that argument is about as relevant as whether Betamax was better than VHS. Whether it's Moor... » read more

Tech Talk: Set-Top Power

By Ed Sperling - 19 Jan, 2015 - Comments: 0

Broadcom's John Redmond, associate technical director for digital video technology, talks with Semiconductor Engineering about what the next-generation set-top boxes will look like and how they will save power. The video was shot at Cadence's Low Power Summit. [youtube vid=Ov2GFrUTzts] » read more

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tag: low power

Tech Talk: Power Tools

How Do We Push The Limits Of Power?

FD-SOI Vs. FinFETs

The Next Generation Of Wearables

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Low Power Trends Toward FinFET

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