Designing Ultra Low Power AI Processors

By Ann Mutschler - 09 Apr, 2020 - Comments: 0

AI chip design is beginning to shift direction as more computing moves to the edge, adding a level of sophistication and functionality that typically was relegated to the cloud, but in a power envelope compatible with a battery. These changes leverage many existing tools, techniques and best practices for chip design. But they also are beginning to incorporate a variety of new approaches tha... » read more

Week In Review: Design, Low Power

By Jesse Allen - 07 Feb, 2020 - Comments: 0

Presto Engineering, an outsourced operations provider to semiconductor and IoT device manufacturers, acquired the DELTA Microelectronics business unit of FORCE Technology. The acquisition adds DELTA's ASIC design and manufacturing to its portfolio. The two companies will retain a strong relationship: FORCE Technology has become a shareholder of Presto Engineering and Juan Farré, FORCE’s CTO,... » read more

Week In Review: Design, Low Power

By Jesse Allen - 24 Jan, 2020 - Comments: 0

Xilinx filed a patent infringement countersuit against Analog Devices, alleging infringement of eight U.S. patents including technologies involving serializers/deserializers (SerDes), high-speed ADCs and DACs, as well as mixed-signal devices targeting 5G and other markets. The counterclaims are in response to Analog Devices' December lawsuit alleging unauthorized use by Xilinx of eight ADI pate... » read more

Three Steps To Faster Low Power Coverage Using UPF 3.0 Information Models

By Madhur Bhargava - 16 Jan, 2020 - Comments: 2

Controlling power has its costs. The added power elements and their interactions make verification of low-power designs much more difficult and the engineer’s job overwhelmingly complex and tedious. Early versions of the Unified Power Format (UPF) provided some relief, but lacked provisions for a standardized methodology for low-power coverage. Ad hoc approaches are error prone and highly ... » read more

Priorities Shift In IC Design

By Ann Mutschler - 16 Jan, 2020 - Comments: 0

The rush to the edge and new applications around AI are causing a shift in design strategies toward the highest performance per watt, rather than the highest performance or lowest power. This may sound like hair-splitting, but it has set a scramble in motion around how to process more data more quickly without just relying on faster processors and accelerators. Several factors are driving th... » read more

Managing Power Dynamically

By Ann Mutschler - 18 Dec, 2019 - Comments: 1

Design teams are beginning to consider dynamic power management techniques as a way of pushing the limits on performance and low power, leveraging approaches that were sidelined in the past because they were considered too difficult to deploy. Dynamic voltage and frequency scaling (DVFS), in particular, has resurfaced as a useful approach. Originally intended to dynamically balance performan... » read more

Optimizing Power And Performance For Machine Learning At The Edge

By Mike Fingeroff - 12 Dec, 2019 - Comments: 0

While machine learning (ML) algorithms are popular for running on enterprise Cloud systems for training neural networks, AI/ML chipsets for edge devices are growing at a triple digit rate, according to Tractica “Deep Learning Chipsets” (Figure 1). Edge devices include automobiles, drones, and mobile devices that are all employing AI/ML to provide valuable functionality. Figure 1: Marke... » read more

CXL Vs. CCIX

By Ed Sperling - 06 Dec, 2019 - Comments: 0

Kurt Shuler, vice president of marketing at ArterisIP, explains how these two standards differ, which one works best where, and what each was designed for. » read more

Better, Not Best

By Brian Bailey - 26 Nov, 2019 - Comments: 0

The semiconductor industry has been lulled into a particular way of thinking by Moore's Law. It is like the age-old joke — you don't have to outrun a bear, you only have to be faster than your companion. The same has held true for designs. There is little to no point being the best, you only have to be good enough to be better than the competition. That sets the bar. Best is also relative.... » read more

Static Verification Of Low Power Designs

By Himanshu Bhatt - 26 Nov, 2019 - Comments: 0

Are there any chips designed today that don’t have limitations on their power consumption? For smartphones and tablets, increasing the time between charges is a clear product differentiator and a frequent design goal. Power consumption is also an issue for Internet-of-Things (IoT) devices, many of which are in inaccessible locations where battery replacement or recharge is difficult. Even com... » read more

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tag: low power

Designing Ultra Low Power AI Processors

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Three Steps To Faster Low Power Coverage Using UPF 3.0 Information Models

Priorities Shift In IC Design

Managing Power Dynamically

Optimizing Power And Performance For Machine Learning At The Edge

CXL Vs. CCIX

Better, Not Best

Static Verification Of Low Power Designs

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