tag: machine learning

Hyperscale HW Optimized Neural Architecture Search (Google)
By Technical Paper Link - 21 Apr, 2023 - Comments: 0

A new technical paper titled "Hyperscale Hardware Optimized Neural Architecture Search" was published by researchers at Google, Apple, and Waymo. "This paper introduces the first Hyperscale Hardware Optimized Neural Architecture Search (H2O-NAS) to automatically design accurate and performant machine learning models tailored to the underlying hardware architecture. H2O-NAS consists of three ... » read more

100G Ethernet At The Edge
By Ed Sperling - 19 Apr, 2023 - Comments: 0

The amount of data is growing, and so is the need to process it closer to the source. The edge is a middle ground between the cloud and the end point, close enough to where data is generated to reduce the time it takes to process that data, yet still powerful enough to analyze that data quickly and send it wherever it is needed. But to make this all work requires faster conduits for that data i... » read more

How Chip Engineers Plan To Use AI
By Ed Sperling - 19 Apr, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss how AI is being used today and how engineers expect to use it in the future, with Michael Jackson, corporate vice president for R&D at Cadence; Joel Sumner, vice president of semiconductor and electronics engineering at National Instruments; Grace Yu, product and engineering manager at Meta; and David Pan, professor in the ... » read more

Nightmare Fuel: The Hazards Of ML Hardware Accelerators
By Steve Roddy - 13 Apr, 2023 - Comments: 0

A major design challenge facing numerous silicon design teams in 2023 is building the right amount of machine learning (ML) performance capability into today’s silicon tape out in anticipation of what the state of the art (SOTA) ML inference models will look like in 2026 and beyond when that silicon will be used in devices in volume production. Given the continuing rapid rate of change in mac... » read more

Using Machine Learning To Increase Yield And Lower Packaging Costs
By Melvin Lee - 11 Apr, 2023 - Comments: 0

Packaging is becoming more and more challenging and costly. Whether the reason is substrate shortages or the increased complexity of packages themselves, outsourced semiconductor assembly and test (OSAT) houses have to spend more money, more time and more resources on assembly and testing. As such, one of the more important challenges facing OSATs today is managing die that pass testing at the ... » read more

Autonomous Driving: End-to-End Surround 3D Camera Perception System (NVIDIA)
By Technical Paper Link - 10 Apr, 2023 - Comments: 0

A new technical paper titled "NVAutoNet: Fast and Accurate 360∘ 3D Visual Perception For Self Driving" was published by researchers at NVIDIA. Abstract "Robust real-time perception of 3D world is essential to the autonomous vehicle. We introduce an end-to-end surround camera perception system for self-driving. Our perception system is a novel multi-task, multi-camera network which takes a... » read more

Overview of Machine Learning Algorithms Used In Hardware Security (TU Delft)
By Technical Paper Link - 09 Apr, 2023 - Comments: 0

A new technical paper titled "A Survey on Machine Learning in Hardware Security" was published by researchers at TU Delft. Abstract "Hardware security is currently a very influential domain, where each year countless works are published concerning attacks against hardware and countermeasures. A significant number of them use machine learning, which is proven to be very effective in ... » read more

Google’s TPU v4 Architecture: 3 Major Features
By Technical Paper Link - 07 Apr, 2023 - Comments: 0

A new technical paper titled "TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings" was published by researchers at Google. Abstract: "In response to innovations in machine learning (ML) models, production workloads changed radically and rapidly. TPU v4 is the fifth Google domain specific architecture (DSA) and its third supercomputer f... » read more

Combination of AI Techniques To Find The Best Ways to Place Transistors on Silicon Chips
By Technical Paper Link - 30 Mar, 2023 - Comments: 0

A new technical paper titled "AutoDMP: Automated DREAMPlace-based Macro Placement" was published by researchers at NVIDIA. Abstract: "Macro placement is a critical very large-scale integration (VLSI) physical design problem that significantly impacts the design power-performance-area (PPA) metrics. This paper proposes AutoDMP, a methodology that leverages DREAMPlace, a GPU-accelerated place... » read more

AI Becoming More Prominent In Chip Design
By Ed Sperling - 27 Mar, 2023 - Comments: 0

Semiconductor Engineering sat down to talk about the role of AI in managing data and improving designs, and its growing role in pathfinding and preventing silent data corruption, with Michael Jackson, corporate vice president for R&D at Cadence; Joel Sumner, vice president of semiconductor and electronics engineering at National Instruments; Grace Yu, product and engineering manager at Meta... » read more

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