tag: Mentor Graphics

The Week In Review: System-Level Design
By Ed Sperling - 06 Dec, 2013 - Comments: 0

Synopsys is closing in on the $2 billion mark, which would set a new record in EDA. The company posted strong financial results for its fiscal Q4 and fiscal 2013. For its fiscal year, revenue was $1.962 billion, up 11.7% from $1.756 billion in fiscal 2012. Net income for the year was $247.8 million, up from $182.4 million. For the most recent quarter, revenue was $504.9 million, up from $454.2 ... » read more

The Path To Power Signoff Is Getting Longer
By Ed Sperling - 06 Dec, 2013 - Comments: 0

Signoff on power used to be a fairly simple check-the-box kind of activity. Even if power budgets weren’t exactly met, they could usually be fixed in future iterations of a chip, whether that involved derivatives or new revs of the same chip. A number of things have changed since the much simpler days of 45/40nm and above, however. Power is now a market differentiator. In many cases, i... » read more

3D-IC Requires Expanded Power Grid Analysis
By Christen Decoin - 05 Dec, 2013 - Comments: 0

At advanced nodes, effective power grid analysis is critical to ensure that the small dimension interconnects can handle current demands without introducing potential failure modes or signal integrity issues. Existing software tools for power analysis need to be extended and enhanced for 2.5D and 3D designs to fulfill new requirements and use models. This article describes some of the needed im... » read more

New Challenges Emerge With FinFETs
By Ed Sperling - 05 Dec, 2013 - Comments: 0

Working at advanced process nodes is always tricky. There are new things to worry about and more rules to deal with initially, yet the promised benefit is improved performance, power and area, or cost. But at the next process node, and the one after that, there are so many variables coming into play that trying to make sense of the PPA equation is becoming much more difficult. Early reports ... » read more

Seven Ways To Improve PPA Before Moving To FinFETs
By Ed Sperling - 05 Dec, 2013 - Comments: 0

Henry Ford wrote in his autobiography, “Any customer can have a car painted any color that he wants so long as it is black.” And for decades, the semiconductor industry has marched to a similar theme set by Moore’s Law. But with the transition to finFETs harder than it first appeared, questions are beginning to pop up that is fueling a new level of confusion. While the growing list of... » read more

Blog Review: Dec. 4
By Ed Sperling - 04 Dec, 2013 - Comments: 0

Mentor’s Harry Foster closes his epic study on functional verification with an interesting insight about the real value of industry studies—new questions. It’s hard to argue with that. Cadence’s Brian Fuller takes a shot at the people taking shots at Amazon’s drone delivery service (the term du jour is robots). It does sound cool, as long as they don’t deliver the kind of payloa... » read more

A Guide To Power-Aware Memory Repair
By Various Writers - 04 Dec, 2013 - Comments: 0

The number of embedded memories contained within an SoC continues to grow rapidly. This growth has driven the need for rethinking manufacturing test strategies as embedded memories represent in most cases a die’s largest contributor to yield loss due to the very large area and density of these regular circuits. A successful memory strategy must incorporate some form of repair methodology in o... » read more

Blog Review: Nov. 27
By Ed Sperling - 27 Nov, 2013 - Comments: 0

Synopsys’ Brent Gregory is looking at real-world experiments to figure out which EDA software is better. Make sure to check out his stats. Cadence’s Brian Fuller interviews two Samsung engineers in a video about the image technology in smart phone cameras and just how far it’s progressed. Hint: Don’t forget to charge your phone on your next vacation. Mentor’s Colin Walls points ... » read more

The Week In Review: System-Level Design
By Ed Sperling - 22 Nov, 2013 - Comments: 0

Synopsys rolled out new non-volatile memory IP that cuts power by 90% and reduces area in half. The company said it accomplished this feat with a single-bit read capability, which can drop read operation down to 0.9 volts and peak current to less than 10 microamps during erase and programming. The target of the ultra-low power IP is RFID and near-field computing ICs. Mentor Graphics posted p... » read more

Is There Light At The End Of Moore’s Tunnel
By Brian Bailey - 22 Nov, 2013 - Comments: 2

Electrons are slow, clumsy and quite easily distracted. They’re slow because it now takes a signal longer to cross a chip than the period of the clock signal. They often don’t travel in straight lines as they collide with other atoms. And electromagnetic interference between adjacent signals can mess with the information they are transferring. On the other hand, light has none of these p... » read more

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