tag: Mentor Graphics

The Week In Review: Oct. 18
By Mark LaPedus - 18 Oct, 2013 - Comments: 0

By Mark LaPedus & Ed Sperling The problems continue with extreme ultraviolet (EUV) lithography. ASML promised to deliver an 80 Watt power source by year’s end. Now, the company said it only will have a 70 Watt source by mid-2014. “We are focusing on reaching the 70 Watts by the middle of next year,” said Peter Wennink, ASML’s CEO, in a conference call to discuss the company’s res... » read more

Approaching IP Quality From Many Angles
By Ann Mutschler - 17 Oct, 2013 - Comments: 0

As SoC design complexity has increased, semiconductor design IP and the industry around it has grown in its level of sophistication. This is great news for the users of that IP whose demands for quality, reliability and other deliverables have also been on the rise. Making sure users have what they need requires close collaboration between the semiconductor foundries, IP providers and of cou... » read more

Reducing The Tapeout Crunch With Signoff Confidence
By Jean-Marie Brunet - 17 Oct, 2013 - Comments: 1

Crunch time—that last six to eight weeks before tapeout. There’s always too much to do, and too little time. No one wants problems at this stage, because problems mean changes, and changes mean delays. At leading-edge nodes, however, we’re running into some new problems that need new solutions. We all know design rule numbers and complexity are going through the roof as we try to use 1... » read more

Improving Design Reliability By Avoiding Electrical Overstress
By Various Writers - 17 Oct, 2013 - Comments: 0

Electrical overstress (EOS) is one of the leading causes of IC failures across all semiconductor manufacturers, and is responsible for the vast majority of device failures and product returns. The use of multiple voltages increases the risk of EOS, so IC designers need to increase their diligence to ensure that thin-oxide digital transistors do not have direct or indirect paths to high-voltage ... » read more

Blog Review: Oct. 16
By Ed Sperling - 16 Oct, 2013 - Comments: 0

Cadence’s Richard Goering follows Si2’s move into SPICE modeling following the acquisition of the Compact Model Council. Combining standards groups is a growing trend these days. Mentor’s Colin Walls points to the demise of reset buttons. You can always trip a circuit breaker, and usually turn off a device by pulling out the battery, but a reset button is simpler. Where did they go? ... » read more

The Week In Review: Oct. 11
By Mark LaPedus - 11 Oct, 2013 - Comments: 0

By Mark LaPedus & Ed Sperling Demand is running high for DRAMs, thanks to last month’s fab fire at Hynix’ China plant. “The impact from Hynix' fab fire seems to be far more extensive than we had originally thought. We now think the factory is most likely up at the earliest by May/June 2014, which certainly provides robust pricing support for DRAM. Hynix is in the process of convertin... » read more

The Brave New World Of FinFETs
By Ed Sperling - 10 Oct, 2013 - Comments: 0

SoCs using 16nm and 14nm finFETs are expected to begin rolling out next year using a 20nm back-end-of-line process. While the initial performance and power numbers are looking very promising, the challenges of designing and building these complex chips are daunting—and there are more problems on the way. First, the good news. Initial results from foundries show a 150% improvement in perfor... » read more

Transient Current Crunch
By Ann Mutschler - 10 Oct, 2013 - Comments: 0

When Intel talks, people listen. So when Intel executive VP Dadi Perlmutter said in a keynote at ISSCC in 2012 that transient power noise was one of the most limiting aspects of the chip design process—and how the package and the board inductance are limiting how low they can take the supply voltage—it showed the gravity of the challenge of effectively managing transient power. Transient po... » read more

On-Chip MCUs Excel At Power Management
By Ann Mutschler - 10 Oct, 2013 - Comments: 0

By Ann Steffora Mutschler When it comes to supplying power to an SoC, there is an increasing trend to make it more intelligent—how to control it more accurately, how it is monitored and how it communicates with different aspects of the chip. Traditional power supply models with analog supplies have less of this control, so a number of engineering teams are considering the use of on-chip m... » read more

The Integrated IP Subsystem: A Converging SoC Solution
By Various Writers - 10 Oct, 2013 - Comments: 0

The consumer device market is witnessing incredible market space convergence between mobile handheld, automotive, and home electronics. IP vendors, engineers, and system design engineers face a multitude of challenges when designing and developing ICs, systems, or subsystems for the next great portable device. The next cell phone for instance, will not only be a multimedia player, but also a de... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy