tag: Mentor Graphics

More Test Needed For Integrated IP
By Ann Mutschler - 26 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler As the use and reuse of design IPs and cores has reached approximately 70% of the content of an SoC, the need for both pre- and post-silicon test has increased. On the pre-silicon side, test comes in the form of verification IP. Driving the addition of more strenuous test approaches on this side is a combination of forces that impact design, noted Tom Hackett, prod... » read more

The Week In Review: Sept. 23
By Mark LaPedus - 23 Sep, 2013 - Comments: 0

By Mark LaPedus For some time, Apple’s iPhones have incorporated a separate RF switch and diversity switch from Peregrine Semiconductor (PSMI). The switches are based on a silicon-on-insulator (SOI) variant called silicon-on-sapphire (SOS). Murata takes Peregrine’s RF switches and integrates them into a module. Doug Freedman, an analyst with RBC Capital, said Apple is no longer using PSMI�... » read more

The Week In Review: Sept. 20
By Ed Sperling - 20 Sep, 2013 - Comments: 0

By Ed Sperling It’s reference flow update time as TSMC prepares to roll out both finFETs and stacked die capabilities, and advanced capabilities at 20nm. The foundry updated its reference flows to include tools and IP from all of the Big Three EDA companies. It added Mentor Graphics’ place and route and DFM tools in its 16nm finFET reference flow, and added a slew of Mentor tools, inclu... » read more

Boson Hunting
By Ed Sperling - 20 Sep, 2013 - Comments: 0

By Ed Sperling It’s not the “God particle” or anything even remotely connected to the formation of the universe. But in particle physics, the powerful forces that keep the tiny particles in an atom confined to a very small space are now coming into much better focus. [caption id="attachment_5772" align="alignnone" width="640"] Source: Cern.ch[/caption] The reason is a combination o... » read more

Mask Data Prep Issues Compounding At 20nm
By Ann Mutschler - 19 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler When it comes to mask data prep—the step in the design and manufacturing flow that occurs just after optical proximity correction (OPC)—challenges have continued to rise with the subsequent moves to smaller geometries. This is driven by the scaling demands of delivering about a 50% area shrink from node to node on a two-year cycle, and thus dictates the lithog... » read more

The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions
By Various Writers - 19 Sep, 2013 - Comments: 0

Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models, in turn, rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. While certain system input variables, such as scanner numerical aperture, can be empirically tuned... » read more

You Ain’t Seen Nothing Yet
By David Abercrombie - 19 Sep, 2013 - Comments: 1

I’ve been talking about double patterning for a long time now in this series of blogs. I thought it might be good to start looking ahead at what is next for multi-patterning (Don’t Panic!). As you may have been hearing or reading, it doesn’t look like EUV lithography is going to be ready for 10nm, and may not even make it for 7nm. This means that alternative methods of extending the exist... » read more

Blog Review: Sept. 18
By Ed Sperling - 18 Sep, 2013 - Comments: 0

By Ed Sperling It’s amazing how irresistible an engineer suddenly becomes when he has an FPGA prototyping board in his hands. Check out the photo of Synopsys’ Mick Posner in Taiwan. Cadence’s Brian Fuller digs into semiconductor startups, why there’s been such a lull, and how new startups are changing. Mentor’s John Day picks out a new product category from TI—inductance to... » read more

The Week In Review: Sept. 16
By Mark LaPedus - 16 Sep, 2013 - Comments: 0

By Mark LaPedus In June, Crucial.com teamed up with Lou Ferrigno to invite all frustrated computer users to submit a short video showing their most fearsome, frustration-filled and computer-induced roar. Each video was evaluated according to a variety of factors, including volume, enthusiasm, perceived distress, frustration, anxiety, irritation and overall hopelessness. The memory module suppl... » read more

The Week In Review: Sept. 13
By Ed Sperling - 13 Sep, 2013 - Comments: 0

By Ed Sperling Cadence unveiled its next-generation emulation platform, greatly boosting the speed by up to 60x for embedded OS verification and by up to 10x for hardware/software verification. Overall, Cadence says the platform doubles verification productivity with a capacity of up to 2.3 billion gates. Cadence also reported that its mixed-signal LP flow allowed Silicon Labs to cut its MCU p... » read more

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