tag: Mentor Graphics

Getting In the Ballpark
By Ann Mutschler - 09 Aug, 2012 - Comments: 0

I admit it; I still have DAC on the brain. Even though attendance may not have been what the exhibitors would have liked to see, the conference is always a fantastic place to discuss ideas and pick up on trends. One topic I discussed with a number of folks are the challenges associated with design today, from the power-performance balance, 3D stacking to new process nodes and complexity, to nam... » read more

Experts At The Table: Multipatterning
By Ed Sperling - 31 Jul, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung El... » read more

DSA Moves To R&D Pilot Lines
By Ed Sperling - 31 Jul, 2012 - Comments: 0

By Mark LaPedus Directed self-assembly (DSA), an alternative lithography technology that makes use of block copolymers, is still in the R&D stage for semiconductor production. But as the exotic patterning technology continues to make astounding progress, there are signs the IC industry is accelerating its efforts to bring DSA from the lab to the fab. In fact, DSA suddenly has become a ... » read more

Looking Into The Future
By Ed Sperling - 31 Jul, 2012 - Comments: 0

Semiconductor Manufacturing & Design sat down with Juan Rey, senior director of engineering for Calibre at Mentor Graphics, about multipatterning, design rules and silicon photonics. [youtube vid=KoH5TwmFWDM] » read more

Experts At The Table: Stacking The Deck
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler There is no doubt 3D stacking brings challenges not only from the design perspective, but also on the tool side. EDA vendors have been working for more than a few years to ready tools for stacked-die designs. How smooth the transition is, however, is a big question mark. Because the approach is new, not all the challenges are fully understood yet. And while most ED... » read more

Routing Congestion Returns
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling Routing congestion has returned with a vengeance to SoC design, fueled by the advent of more third-party IP, more memory, a variety of new features, as well as the inability to scale wires at the same rate as transistors. This is certainly not a foreign concept for IC design. The markets for place and route tools were driven largely by the need to automate this kind of operat... » read more

Smarter Co-design With Models
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler IC, package and PCB co-design methodologies are starting to be adopted by semiconductor companies. However, the existing die abstract file used in these flows to exchange data between the IC designer and the downstream package design team may not contain enough detail to drive advanced planning and optimization with the package and PCB interfaces. Engineering teams... » read more

Motorcycle Diaries
By Jon McDonald - 26 Jul, 2012 - Comments: 0

By Jon McDonald I recently had reason to add another vehicle to my household. My son is starting to drive, so he's taking my car. Instead of another car I decided to get a motorcycle. I have had a couple, but it's been a few years. After much browsing I decided on a Ducati, I picked it up a few weeks ago. It has an impressive number of user adjustable electronic controls, everything from AB... » read more

Achieving Fast And Accurate Extraction Of 3D-IC Layout Structures
By Various Writers - 26 Jul, 2012 - Comments: 0

The electronics industry is devoting a lot of energy to exploring “More than Moore’s Law” approaches that drive continued value scaling through system integration, rather than (or in addition to) shrinking transistors. One of the most promising techniques is the creation of 3D-ICs using TSV structures. However, accurately modeling a 3D multi-die system requires tools that extract precise ... » read more

More Design Rules Ahead
By Ed Sperling - 25 Jul, 2012 - Comments: 0

By Ed Sperling & Mark LaPedus For those companies that continue to push the limits of feature shrinkage, designs are about to become more difficult, far more expensive—and much more regulated. Two converging factors will force these changes. First, the limits of current 193nm immersion lithography mean companies now must double pattern at 20nm, and potentially quadruple pattern at 14n... » read more

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