DSA Moves To R&D Pilot Lines

Other options being explored as industry awaits delivery of EUV. But even with EUV, other solutions may be viable.

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By Mark LaPedus
Directed self-assembly (DSA), an alternative lithography technology that makes use of block copolymers, is still in the R&D stage for semiconductor production.

But as the exotic patterning technology continues to make astounding progress, there are signs the IC industry is accelerating its efforts to bring DSA from the lab to the fab. In fact, DSA suddenly has become a viable pattering option at 10nm, and maybe even sooner.

At the recent Semicon West trade show in San Francisco, for example, Intel disclosed that DSA is one of many options in its lithography roadmap. “We are working on multiple solutions in parallel,” said Yan Borodovsky, senior fellow and director of advanced lithography at Intel. “The rate of progress for DSA is comparable with the rate of progress for immersion lithography (at a similar timeframe). It’s that fast. The key issue with DSA is defects. That is still an open question.”

To help determine if DSA is ready for prime time, two R&D organizations, CEA-Leti and IMEC, will soon take delivery of a new class of wafer track gear aimed to speed up the development times for their respective 300mm DSA pilot lines. Unlike today’s IC manufacturing process, which revolves around lithography, the key tool to bring DSA into production is a conventional wafer track system.

The two main track suppliers, Sokudo Co. Ltd. and Tokyo Electron Ltd. (TEL), will ship specially-configured DSA coater/developer systems to Leti and IMEC, respectively. And in fact, Sokudo plans to ship another unit to an undisclosed semiconductor maker.

DSA changes the litho game
At present, chipmakers are expected to use 193nm immersion lithography and double-patterning at 20nm. Then, at 14nm and 10nm, the industry would like to insert extreme ultraviolet (EUV) lithography. If EUV misses those windows, the industry will extend 193nm immersion and move to a more complex multi-patterning scheme. Maskless and nanoimprint are also candidates, but those technologies are behind.

The wild card is DSA. DSA makes use of existing lithography tools. When used in conjunction with a pre-pattern that automatically directs the orientation of the block copolymers, DSA can reduce the pitch of the final printed structure. Using 193nm immersion, DSA has demonstrated the ability to print images down to 12.5nm—without the need for multi-patterning. DSA could extend 193nm lithography beyond 10nm, eliminate multi-patterning, and push out EUV.

Some believe that DSA could get inserted as early as the 14nm node. Moshe Preil, manager of emerging lithography and tools at GlobalFoundries, said a more realistic insertion point for DSA is 10nm. “It’s really too late to insert DSA at 14nm,” Preil said.

The key challenges for DSA include defect densities, line-edge roughness and the lack of next-generation copolymers. Current block copolymers based on today’s poly (MMA-co-styrene) materials do not scale beyond 11nm.

There is also a need to develop a new design environment for DSA. Potentially, the technology could turn out to be “a credible path for some layers,” said Juan Rey, senior director of engineering for Calibre at Mentor Graphics. “In general, the models are very complex for DSA. We have not seen enough proof that the models can be applicable.”

R&D firms bring up DSA
To iron out the bugs and help determine if DSA is indeed viable, CEA-Leti, IBM, Intel, GlobalFoundries, IMEC and others are exploring the technology. Earlier this year, IMEC claimed to have installed the world’s first 300mm DSA process line. AZ Electronic Materials makes the copolymers for IMEC’s line, while TEL provides the track systems.

In IMEC’s DSA flow, a guide is patterned using conventional lithography. Then, the guide goes through a trim etch step, followed by a resist strip, and a coat and rinse process. The guide is then coated with block copolymers, which are then annealed, etched and clean.

Line features as small as 12.5nm and 25nm contact holes have been patterned on 300mm substrates using DSA at IMEC, said Ben Rathsack, member of the technical staff at TEL. Soon, TEL will provide IMEC with a new track system geared for DSA production.

Meanwhile, in June, CEA-Leti set up its own 300mm DSA pilot line. The line is using Sokudo’s RF3 track system and copolymers from Arkema. The line is based on a graphoepitaxy process flow. In this flow, a guide is patterned using conventional lithography. Using a track system, the guide is spin-coated, rinsed and spin-coated again with copolymers. The copolymers self-assemble and the guide is then etched.

With this process, DSA has demonstrated 15nm lines and spaces, said Serge Tedesco, lithography program manager at CEA-Leti. “DSA is a complementary lithography that could get inserted as early as the 14nm node,” Tedesco said. “One of the key problems with DSA is metrology.”

Later this year, CEA-Leti is expected to upgrade its DSA line by installing Sokudo’s new Duo track system. “The Duo track performs neutral layer spin-coat and bake to prepare the wafer surface for the block co-polymers. The pattern forming the self-assembly process (takes place in a) high temperature bake step,” said Charles Pieczulewski, director of strategic marketing for Sokudo. Sokudo is a subsidiary of Dainippon Screen. Applied Materials itself has a 19% stake in Sokudo.

“We anticipate a pilot production transition for DSA in 2013-2014, with volume production in 2015 for the 10nm/7nm nodes as a complementary lithography for select via shrinks and/or pitch multiplication line-and-space patterns,” Pieczulewski said.

Intel’s plans
Chipmakers also are taking a hard look at DSA. For 22nm and 14nm, Intel will continue to use 193nm immersion. Then, the company is looking at two options at 10nm. One option is to use EUV for the critical layers. If EUV is not ready, the second option is to use 193nm immersion with multi-patterning.

In another option, Intel also could implement what it calls “complementary lithography.” In this process, there are two steps, gratings and line cuts, to pattern designs. Using a 1-D gridded design rule (GDR) layout, 193nm immersion will be able to print the grating-like patterns.

The next step is to use spacer technology to double, triple or quadruple line density. The big question is how to cut the gratings. There are a number of options to perform this step: 193nm immersion; 193nm immersion plus DSA; EUV; or direct-write e-beam.

Each technology has its advantages and disadvantages. The ultimate decision for “high-volume manufacturing depends on the defects and cost-of-ownership,” Borodovsky said.

In a 40nm pitch scenario, for example, the gratings could be handled by 193nm immersion in one mask step. But it would take four additional masks to handle the cuts using 193nm immersion—for a total of five mask steps, he said.

In theory, EUV and direct-write could be less expensive than 193nm in this step. “EUV is more mature,” he said. In a 40nm pitch scenario with EUV, it would only require two mask steps: One for the gratings and one for the cuts.

Still, EUV suffers from a lack of power sources. It also requires slower resists than what are available today. “Photon shot noise statistics alone leads to the conclusion that resists capable of meeting 20nm contacts, and cuts might need to be sufficiently slower than the current targets,” he said.

Yet another option is a combination of 193nm immersion and DSA to do the cuts. “DSA will be used extensively if we can solve the defect issues,” he said. “It’s impossible to say at this point (whether or not DSA will work). Within the next year, people will reach a conclusion.”