tag: Mentor Graphics

High Speed PCB Layout: Physical Design Issues Of Highspeed Interfaces
By Various Writers - 28 Jun, 2012 - Comments: 0

Moore’s law, applied to data rates, has pushed PCB circuits so fast that the layout becomes part of the circuit. In designs such as DDR3 and PCIe, the fastest memory and high-speed serial performance comes with very specific physical layout requirements that are not obvious. Unless you are thinking like an RF designer, there are many unexpected challenges to a successful high-speed layout. A ... » read more

Experts At The Table: IP Subsystems
By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss the transition to IP subsystems with Kevin Meyer, vice president of design enablement strategy and alliances at GlobalFoundries; Steve Roddy, vice president of marketing at Tensilica; Mike Gianfagna, vice president of marketing at Atrenta; and Adam Kablanian, CEO of Memoir Systems. What follows are excerpts of that con... » read more

Experts At The Table: Multipatterning
By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung Ele... » read more

Fallback Plans
By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler With EUV lithography missing a few deadlines already, the semiconductor industry has begun to search for alternatives. None of these solutions is simple, of course, and it’s questionable whether they’re even economically viable. And even if EUV is ready for mass production by 14nm, there are new challenges that have to be dealt with—particularly in the space... » read more

Model-Based Double-Dipole Lithography For Sub-30nm Node Device
By Various Writers - 26 Jun, 2012 - Comments: 0

As the optical lithography advances into the sub-30nm technology node, the various candidates of lithography have been discussed. Double dipole lithography (DDL) has been a primary lithography candidate due to the advantages of a simpler process and a lower mask cost compared to the double patterning lithography (DPL). However, new DDL requirements have been also emerged to improve the process ... » read more

Experts At The Table: Improving The Efficiency Of Software
By Ed Sperling - 22 Jun, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Design sat down to talk about how to write better software with Jan Rabaey, Donald O. Pederson Distinguished Professor at the University of California at Berkeley; Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Emily Shriver, research scientist at Intel; Alan Gibbons, principal engineer at Synopsys; and Dav... » read more

Power Shift
By Ed Sperling - 14 Jun, 2012 - Comments: 0

By Ed Sperling For the past decade, most of the real gains in energy efficiency were developed for chips inside mobile electronics because of the demand for longer battery life. Dark silicon now represents the majority of mobile devices, multiple power islands are commonplace to push many functions into deep sleep, and performance is usually the secondary concern for most applications. Whil... » read more

Experts At The Table: Improving The Efficiency Of Software
By Ed Sperling - 14 Jun, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Design sat down to talk about how to write better software with Jan Rabaey, Donald O. Pederson Distinguished Professor at the University of California at Berkeley; Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Emily Shriver, research scientist at Intel; Alan Gibbons, principal engineer at Synopsys; and Da... » read more

Efficiency Vs. Accuracy
By Barry Pangrle - 14 Jun, 2012 - Comments: 0

By Barry Pangrle If all you have is a hammer, everything looks like a nail. I wrote an article, Power vs. Accuracy, last year that discussed tradeoffs between power and accuracy for different applications. It turns out that for a number of processing applications, if every bit isn’t perfect, the impact on the final result might not be all that great. Anyone performing financial analytical... » read more

Executive Briefing: Trillion-Gate Designs
By Ed Sperling - 31 May, 2012 - Comments: 0

Wally Rhines, CEO of Mentor Graphics, talks with System-Level Design about what's needed for trillion-gate designs, the increasing demands of verification and emulation, new tools for stacked die and the trend toward designing for the enterprise. [youtube vid=pQs1qNkFvVo] » read more

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