tag: Mentor Graphics

Getting Ready For 20nm
By Ed Sperling - 29 May, 2012 - Comments: 0

By Ed Sperling and Mark Lapedus Despite hurdles in getting 28nm rolling and predictions that process technology will stick around for years to come, there appears to be rapidly growing interest in 20nm—at least from the design side. This is significant for a couple reasons. First, for most companies 20nm will be the first encounter with double patterning because EUV still is not viable—... » read more

The Hidden Costs Of Directed Self-Assembly
By Ed Sperling - 29 May, 2012 - Comments: 2

By Mark LaPedus Directed self-assembly (DSA) has been billed by some as a potential paradigm shift in semiconductor manufacturing, but it may not turn out to be quite the panacea its proponents suggest—or at least not yet. There are many questions surrounding DSA, an alternative lithography technology that makes use of block copolymers to enable fine pitches. Key among those questions ar... » read more

Finding And Eliminating Hot Spots
By Various Writers - 29 May, 2012 - Comments: 0

With the continuous development of today’s technology, IC design becomes a more complex process. The designer now not only takes care of the normal design and layout parameters as usual, but also needs to consider the process variation impact on the design to preserve the same chip functionality with no failure during fabrication. In the current process, schematic designers go through extensi... » read more

The Brave New World Of Modeling TSVs
By Ed Sperling - 26 May, 2012 - Comments: 0

By Ann Steffora Mutschler With 2D ICs the prevailing notion has been that wire parasitics are relatively self-contained with the exception of very advanced designs running at hundreds of gigahertz. For the most part, the package designer and IC designer lived in their own separate worlds. With the advent of chip stacking using through silicon vias (TSVs), those worlds are being thrust together... » read more

Packaging Tradeoffs More Complex Than Ever
By Ed Sperling - 24 May, 2012 - Comments: 0

By Ann Steffora Mutschler Driven by high-speed interfaces, the demand for TSVs and the complexities that new process nodes bring, older packaging technologies like wirebonding can’t keep up. The latest and greatest flip chip technologies offer much more flexibility, but at a cost. As such, the package plays a larger role than ever in determining system specifications because, depending o... » read more

EDA’s Cloudy Vision
By Ed Sperling - 24 May, 2012 - Comments: 0

By Ann Steffora Mutschler Since the dawn of EDA, the industry has largely operated under a traditional software distribution model whereby the customer would run the software it licensed on its own hardware equipment. With the sophistication of advanced IT management techniques as well as education surrounding “The Cloud,” it may be safe to predict that engineers in the not-to-distant futu... » read more

Getting Ahead Of Yourself
By Jon McDonald - 24 May, 2012 - Comments: 0

By Jon McDonald Recently we've been doing some minor remodeling in our house—nothing requiring major contractors. It’s mostly smaller things that unfortunately require a significant amount of personal involvement. Over the course of the past few weeks we've had a number of "projects" that we've started, then had to undo what was done because we were interfering with another area of work. M... » read more

Understanding Via Effects
By Various Writers - 24 May, 2012 - Comments: 0

As the demand for fast computation and information transmission has increased dramatically in recent years, many designs have boards with signals operating in the multiple-Gbps range. Advanced memory designs are targeting over 10 Gbps data rates while the SERDES standard is moving toward 25-28 Gbps. With the signal speed changes come the new challenges of solving design issues never seen before... » read more

Technology Crossover Ahead
By Ed Sperling - 18 May, 2012 - Comments: 0

The attention showered upon NVM Express these days by both Synopsys (verification IP) and Cadence (subsystem) is significant. It’s the first significant opening in the enterprise computing space to emerge in years, and this is a market in which efficiency and performance are both measured and fully recognized. While SoC developers in the mobile space continue to develop power-management ca... » read more

Experts At The Table: Hardware-Software Co-Design
By Ed Sperling - 11 May, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss hardware-software co-design with Frank Schirrmeister, group marketing director for Cadence’s System and Software Realization Group; Shabtay Matalon, ESL market development manager at Mentor Graphics; Kurt Shuler, vice president of marketing at Arteris; Narendra Konda, director of hardware engineering at Nvdia; and Jack Greenbaum, direct... » read more

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