Moore’s Law Revisited


By Ed Sperling The push to 20nm and beyond is creating some interesting gyrations in the EDA industry. While tools vendors continue to work on tools for the latest process nodes, they’re also taking some significant sidesteps. The first to publicly recognize a shift is under way was Cadence, which last year issued its EDA 360 manifesto. The strategy is to continue investing in existing to... » read more

Applying Rules Differently


By Jon McDonald Over the past few months I’ve worked with a number of customers on new designs. Thinking about how these designs were evolving in the various organizations led me to an interesting epiphany related to the application of Gall’s Law to system design. Gall's Law is a rule of thumb from John Gall's Systemantics: How Systems Really Work and How They Fail: “A complex system ... » read more

Experts At The Table: Yield Issues


By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss yield with Amiad Conley, technology marketing manager for yield and process control at Applied Materials; Cyrus Tabery, senior member of the GlobalFoundries technical staff for lithography development and DFM; Brady Benware, engineering manager for diagnosis and yield at Mentor Graphics, and Ankush Oberai, general man... » read more

Double Patterning Requires a Double Take


By David Abercrombie As the unstoppable progression of Moore’s law has driven the semiconductor technology roadmap farther and farther below 1 µm, a steady stream of engineering marvels has been required to produce leading edge chips. For most of that roadmap, the enabling engineering solutions were on the processing side. For instance, the development of i-line, then KrF and ArF light so... » read more

Widening The Channels


By Ed Sperling Wide I/O—both as a specific memory standard and as a generic approach for on-chip networking—has been looked at for the past couple of chip generations as a way of improving SoC performance. Increasingly, it also is being used as a key strategy for reducing energy consumption. Wide I/O refers to a number of different approaches in on-chip networking, ranging from through-... » read more

The Shocking Side Of 3D


By Ann Steffora Mutschler The pesky static charge that builds up on your clothing when you forget the dryer sheet is more than just a nuisance when it comes to manufacturing ICs. Add 3D structures and process scaling to the mix and the challenge of adequately protecting those devices grows significantly. While this problem used to be largely an afterthought, the charged-device model type of... » read more

Core Power


By Barry Pangrle What type of core should I choose if I want to be really power-efficient? That’s an interesting question. The answer that a lot of people will hate to hear is that it depends. Probably the first question that needs to be answered is, what does power-efficient mean to you and how power-efficient do you really want to be? Most people can’t wait forever for a result to be ... » read more

The Growing Importance Of Subsystems


By Ed Sperling A growing reliance on third-party IP is beginning to expand well beyond just IP blocks and into full subsystems, opening significant growth opportunities for companies competing in this market as well as enormous business and technical challenges. The IP market is ripe for this kind of convergence. Complexity at advanced process nodes coupled with time-to-market demands has e... » read more

EDA Forecast: More Clouds


By Ed Sperling Design engineers and EDA vendors used to scoff at the idea of cloud-based tools, but no one is scoffing anymore. A decade after the idea of renting tools online fell flat, largely due to security concerns by chipmakers, all three of the major EDA players and some smaller rivals are taking cloud-based solutions very seriously again. There are several reasons for this change... » read more

The Missing Link


By Jon McDonald When something comes up once it may be an anomaly, but when the same thing comes up multiple times in a short period of time there's a good chance it is a more general trend. At Mentor we have tools focused on Systems Engineering and UML/SysML, as well as SystemC ESL/TLM focused tools. We have invested effort in integrating the tool flows, but I had not seen significant driv... » read more

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