tag: Mentor Graphics

The Missing Link
By Jon McDonald - 23 Feb, 2011 - Comments: 0

By Jon McDonald When something comes up once it may be an anomaly, but when the same thing comes up multiple times in a short period of time there's a good chance it is a more general trend. At Mentor we have tools focused on Systems Engineering and UML/SysML, as well as SystemC ESL/TLM focused tools. We have invested effort in integrating the tool flows, but I had not seen significant driv... » read more

Experts At The Table: 3D Stacking
By Ed Sperling - 14 Feb, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice pre... » read more

No More Netlist Hacking
By Ed Sperling - 10 Feb, 2011 - Comments: 0

By Ann Steffora Mutschler Prior to availability of advanced physical verification tools, it was not uncommon for engineering teams to hack netlists. It sounds very clandestine, but was done out of the need to get detailed information on particular areas of the chip suspected to be a problem. Performing electrical rules checks (ERC) to improve the correctness and reliability of IC designs b... » read more

Power vs. Accuracy
By Barry Pangrle - 10 Feb, 2011 - Comments: 0

By Barry Pangrle So, how much energy are you willing to expend to be accurate? The question is one that chip designers face more often than they probably realize. The first question really is, ‘How accurate do you need to be?’ Whether it is test coverage, verification coverage, signal-to-noise ratio, or error-correcting codes, the list is seemingly endless. Variability in the environmen... » read more

Manufacturing Closure with Calibre InRoute and Olympus-SoC
By Various Writers - 10 Feb, 2011 - Comments: 0

Achieving manufacturing signoff is getting more difficult at each node due to significant manufacturing limitations and variability. This paper from Mentor Graphics describes the physical signoff challenges seen in advanced node designs. It then demonstrates how the Calibre InRoute platform provides faster and more reliable DRC/DFM signoff by using the Calibre verification and DFM platform to d... » read more

Metric Pitch BGA And Micro BGA Routing Solutions
By Various Writers - 08 Feb, 2011 - Comments: 0

The following paper provides Via Fanout and Trace Routing solutions for various metric pitch Ball Grid Array Packages. Note: the “metric” dimensions are the ruling numbers. To solve the metric pitch BGA dilemma, one should have a basic understanding of the metric feature sizes for: BGA Ball Sizes and BGA Land Pattern Pad Construction BGA Via Anatomy Trace/Space Trace and Via Routi... » read more

DFM: Out of the Spotlight and Into the Trenches
By David Abercrombie - 03 Feb, 2011 - Comments: 0

By Joe Davis and David Abercrombie The year is 2006. Everywhere you look, the phrase “Design for Manufacturing” or its acronym, DFM, is being brandished as if it were the banner of some brave new army of chip designers. “DFM is the solution to discontinuity issues at 65 nm.” “Traditional boundaries between design and manufacturing will vanish.” Articles and papers discussing DFM ... » read more

Connecting System-Level Flows To Implementation Tools
By Ed Sperling - 27 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler With the complexity explosion occurring in SoC design today, there is a relentless force to push design decisions further up in terms of abstraction. Resolving issues at the gate level is not possible any more because there just isn’t enough time or resources. Further, the resulting design may not even be competitive because optimization at the gate level can leave ... » read more

Tailoring IP, Tools And Flows
By Ed Sperling - 27 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler As SoC and system complexity rises continually and software drives much more in a system, specific vertical application areas will require tailored IP and tool flows to allow designers to meet time-to-market demands. Today, many systems are designed around a platform, which contains most of the STAR IP—processors, GPUs, memory controllers, interconnects, memory s... » read more

Connecting System-Level Flows To Implementation Tools
By Ed Sperling - 27 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler With the complexity explosion occurring in SoC design today, there is a relentless force to push design decisions further up in terms of abstraction. Resolving issues at the gate level is not possible any more because there just isn’t enough time or resources. Further, the resulting design may not even be competitive because optimization at the gate level can leave ... » read more

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