tag: Mentor Graphics

Will The Chip Work?
By Ed Sperling - 19 Oct, 2015 - Comments: 1

IP is getting better, but the challenges of integrating it are getting worse. As the number of IP blocks in SoCs increases at each new process node, so does the difficulty of making them all work together. In some cases, this can mean extra code and a slight performance hit on power and performance. In other cases, it may require more drastic measures, ranging from a re-spin to a new archite... » read more

The Week In Review: Design/IoT
By Jesse Allen - 16 Oct, 2015 - Comments: 0

M&A Continuing to seek economies of scale in the IP industry, VeriSilicon and Vivante are combining forces. "This transaction creates an extensive semiconductor IP portfolio that will now include GPU cores, vision image processors, digital signal processors, video codecs, mixed signal IP and foundry foundation IP," said Wayne Dai, VeriSilicon chairman, president and CEO. The merged compa... » read more

Analog Meets Power In Standards Groups
By Ann Mutschler - 15 Oct, 2015 - Comments: 4

While the topic of language [getkc id="13" comment="Standards"] might be cringe-worthy for some, there is some noteworthy work underway in this area—particularly where power and analog meet paths. There are four main standards here: Verilog-A and Verilog-AMS VHDL-AMS SystemC-AMS SystemVerilog-AMS SystemVerilog-AMS is the newcomer, and while the standard won't be available for ... » read more

Gaps In Performance, Power Coverage
By Brian Bailey - 15 Oct, 2015 - Comments: 0

The semiconductor industry always has used metrics to define progress, and in areas such as functional verification significant advances have been made. But so far, no effective metrics have been developed for power, performance, or other system-level concerns, which basically means that design teams have to run blind. On the plus side, the industry has migrated from the use of code coverage... » read more

Raising The IQ Of Your MEMS-Based IC Design Flow
By Nicolas Williams - 15 Oct, 2015 - Comments: 0

By Nicolas Williams and Qi Jing Internet of Things (IoT) applications depend on smart objects that interact with the real world. So your IoT project is likely to contain ICs that integrate micro electro-mechanical systems (MEMS), such as accelerometers, pressure sensors, motors, and microphones that acquire data for analysis. These projects are finding their way into automobiles, phones, and... » read more

Full-Circuit ADC Verification With Analog FastSPICE
By Mentor, a Siemens Business - 14 Oct, 2015 - Comments: 0

Analog to Digital Converters (ADCs) are critical components in high-speed, high-resolution applications where an analog or RF signal has to be processed, stored, or transported in digital form. ADC performance requirements vary by application and include resolution, dynamic range, linearity, power consumption, speed, bandwidth, SNDR (Signal-to-Noise and Distortion Ratio), and ENOB (Effective Nu... » read more

Blog Review: Oct. 14
By Jesse Allen - 14 Oct, 2015 - Comments: 1

Rambus' Aharon Etengoff explores how new optical interfaces are aiding the burgeoning field of optogenetics, which combines genetic targeting of specific neurons or proteins with optical technology to study living neural circuits. Anand Shirahatti, Divyang Mali, and Naveen G of Synopsys team up to explain three features that make the MIPI UniPro mobile interconnect stand out, along with the ... » read more

Security In 2.5D
By Ed Sperling - 12 Oct, 2015 - Comments: 2

The long-anticipated move to 2.5D and fan-outs is raising some familiar questions about security. Will multiple chips combined in an advanced package be as secure as SoCs where everything is integrated on the same die? The answer isn't a simple yes or no. Put in perspective, all chips are vulnerable to [getkc id="253" kc_name="side channel attacks"], hacking of memory—a risk that increases... » read more

High-Speed Systems Need High-Speed Parts For Prototyping
By Rich Wawrzyniak - 12 Oct, 2015 - Comments: 0

One of the ironies of prototyping for high-speed system design using FPGAs is that in the past most FPGAs did not run at the speeds required by the end system. Many of these FPGAs today have high speed SerDes channels used for communicating with other elements of the system at close to the speeds specified by the designer. Unfortunately most of the FPGAs used for the prototyping phase of the sy... » read more

The Week In Review: Design/IoT
By Jesse Allen - 09 Oct, 2015 - Comments: 0

Imec and Cadence completed the first tapeout of a 5nm test chip. Using a processor design, the companies taped out a set of designs using EUV lithography as well as Self-Aligned Quadruple Patterning for 193i lithography, where metal pitches were scaled from the nominal 32nm pitch down to 24nm to push the limit of patterning. Tools Synopsys folded in recent acquisition Atrenta's testabilit... » read more

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