tag: Mentor Graphics

Internet Of Things Design Considerations For Embedded Connected Devices
By Mentor, a Siemens Business - 07 May, 2015 - Comments: 0

Embedded connectivity has been around since the early days of M2M. But what is new are the many complexities and emerging standards embedded system developers need to know if they are to design the latest IoT device. This paper delves into many of the key considerations developers need to know and discusses the critical areas of IoT security and connectivity along with the importance of a prove... » read more

Blog Review: May 6
By Jesse Allen - 06 May, 2015 - Comments: 0

How do you choose between bulk planar transistors, FinFETs, and FD-SOI? Cadence's Richard Goering got some answers during a session at the Electronic Design Process Symposium. Check out the Q&A in the second part, too. Synopsys' Michael Posner tackles a question about the differences between a prototyping bridge and hybrid prototypes and the limitations each has to solve various kinds of... » read more

Week 47: The Yin And Yang of DAC
By Anne Cirkel - 01 May, 2015 - Comments: 0

In one of my early blog posts I explained that DAC is owned by three non-profit societies: ACM, IEEE/CEDA and EDAC. While the executive committee right now is working on a successful 52nd DAC, planning for future events has already started. Future locations are usually booked years in advance as most of convention center and hotel contracts are signed at least 18 months out. The financial liabi... » read more

The Week In Review: Design/IoT
By Jesse Allen - 01 May, 2015 - Comments: 0

Tools Cadence released the new debug platform Indago, with the aim of reducing the time to identify bugs in a design by up to 50 percent compared to traditional signal- or transaction-level debug methods. Included are three debugging apps that provide an integrated debug solution for testbench, verification IP, and hardware/software debug for SoC designs. Mentor Graphics announced three n... » read more

Blog Review: April 29
By Jesse Allen - 29 Apr, 2015 - Comments: 0

Start your engines. At the Western US Freescale Cup, ARM's Sadanand Gulwadi had a front-row seat to the ingenuity displayed in autonomous model car racing. From turning an abandoned factory into the world's largest indoor farm to the millions invested in mining passing asteroids, Ansys' Bill Vandermark celebrates a week of Earth Day with his top five picks to read. "There is no Department... » read more

Week 46: Don’t Be Late
By Anne Cirkel - 24 Apr, 2015 - Comments: 0

Last year we moved DAC’s official opening session from Tuesday to Monday. The move makes perfect sense as there is much on the Monday schedule, including tutorials as well as the designer and IP track sessions. The opening session has always been special at DAC. It is the most popular general session as various awards are given out that day too. This is how it works: Throughout the year A... » read more

The Week In Review: Design/IoT
By Jesse Allen - 24 Apr, 2015 - Comments: 0

Mergers & Acquisitions Synopsys continued expansion into the software security market with the acquisition of Codenomicon. The Finnish company was in the headlines this time last year when it discovered the Heartbleed bug during product testing. Tools Mentor Graphics released Calibre xACT, a parasitic extraction platform which automatically optimizes extraction techniques based on ... » read more

The Auto Industry Taking Things Into Their Own Hands
By Mathew Clark - 23 Apr, 2015 - Comments: 0

A new standard is here! I can hear a collective groan, but I suggest we quiet down and see what this new direction has to offer. When Audi AG, BMW AG, Daimler AG, Porsche AG, and Volkswagen AG get together to work up a document, there is a shift happening. Although this standard is not out-of-the-oven-fresh, it will mean a change in the industry in the near future. But before I continue, I want... » read more

What Not To Verify
By Ann Mutschler - 23 Apr, 2015 - Comments: 0

It is well understood that [getkc id="10" kc_name="verification"] is all about mitigating and managing risk, and success here begins with a good verification planning process. During the planning process, the project team creates a list of specific design functions and use cases that must be verified—and they identify the technique used to verify each specific item on the list. That list c... » read more

What EDA’s Big 3 Think Now
By Ed Sperling - 23 Apr, 2015 - Comments: 0

In the past two months the CEOs of Cadence, Synopsys and Mentor Graphics delivered their annual high-level messages to their respective user groups. Semiconductor Engineering attended all of the speeches at these conferences, as it did in 2014 (see story here). From a high level, the big issues for CEOs last year were Moore's Law, the costs of design, the impact of low power, and business-... » read more

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