tag: Mentor

Blog Review: May 3
By Jesse Allen - 03 May, 2023 - Comments: 0

Synopsys' Thomas Andersen considers the requirements of AI-optimized chips that are resulting in exploration of different memory configurations, different types of memory, and different types of processor technologies and software components. Cadence's Girish Vaidyanathan considers the role of hierarchy and partitioning in custom design and looks at how a virtual hierarchy allows layout desi... » read more

AI Adoption Slow For Design Tools
By Brian Bailey - 01 May, 2023 - Comments: 0

A lot of excitement, and a fair amount of hype, surrounds what artificial intelligence (AI) can do for the EDA industry. But many challenges must be overcome before AI can start designing, verifying, and implementing chips for us. Should AI replace the algorithms in use today, or does it have a different role to play? At the end of the day, AI is a technique that has strengths and weaknesses... » read more

Week In Review: Semiconductor Manufacturing, Test
By Karen Heyman - 28 Apr, 2023 - Comments: 0

The U.S. Commerce Department  launched Chips.gov, a website that covers all aspects of the CHIPS Act, including funding opportunities and job openings. In similar vein, Intel CEO Pat Gelsinger focused on the future of semiconductor manufacturing in America in a talk at MIT. Intel has committed to expanding semiconductor manufacturing in the U.S., including spending an initial $20 billion on ne... » read more

Week In Review: Design, Low Power
By Jesse Allen - 28 Apr, 2023 - Comments: 0

The National Institute of Standards and Technology (NIST) outlined its plan for a National Semiconductor Technology Center (NSTC) to be created using a share of the $11 billion in funds from the CHIPS Act marked for research and development. While a large portion of the CHIPS Act investment is set to boost U.S. fabs and manufacturing capabilities, the NSTC aims to also support the design side, ... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 28 Apr, 2023 - Comments: 0

Pervasive computing Renesas introduced a narrowband Internet of Things (NB-IoT) chipset and dev kit for the Indian market. The LTE NB-IoT modem chipset, the RH1NS200, was designed for Indian telecommunications carriers by targeting bands 1,3, 5 and 8 and by following India’s carrier-approved LTE protocol stack and software suite. Low power usage is built in — it has a low Power Saving Mode... » read more

EDA Makes A Frenzied Push Into Machine Learning
By Ed Sperling - 27 Apr, 2023 - Comments: 0

Machine learning is becoming a competitive prerequisite for the EDA industry. Big chipmakers are endorsing and demanding it, and most EDA companies are deploying it for one or more steps in the design flow, with plans to add much more over time. In recent weeks, the three largest EDA vendors have made sweeping announcements about incorporating ML into their tools at their respective user eve... » read more

True 3D-IC Problems
By Brian Bailey - 27 Apr, 2023 - Comments: 0

Placing logic on logic may sound like a small step, but several problems must be overcome to make it a reality. True 3D involves wafers stacked on top of each other in a highly integrated manner. This is very different from 2.5D integration, where logic is placed side-by-side, connected by an interposer. And there are some intermediate solutions today where significant memory is stacked on l... » read more

Designing For In-Circuit Monitors
By Ann Mutschler - 27 Apr, 2023 - Comments: 0

In every application space the semiconductor ecosystem touches, in-circuit monitors and sensors are playing an increasing role in silicon lifecycle management and concepts around reliability and resiliency — both during design as well as in the field. The combination of true system-level design, in/on-chip monitors, and improved data analysis are expected to drastically improve reliability... » read more

Easy-To-Use Reliability Checks Throughout The Design Cycle From IP To Full-Chip Tapeout
By Hossam Sarhan - 27 Apr, 2023 - Comments: 0

By Hossam Sarhan and Alexandre Arriordaz With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff verification is no longer practical for design teams. There is a constant push to shift targeted verification activities “left” to earlier stages in the design flow. Finding and eliminating selected errors earlier during design and implementation, wh... » read more

Pre-Layout, Post-Layout Circuit Reliability
By Siemens EDA - 26 Apr, 2023 - Comments: 0

With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff verification to check design reliability is no longer practical for design teams. Designers must now apply reliability verification checks throughout the design flow, from intellectual property (IP) level to full-chip level, to ensure they meet tapeout schedules while confirming design reliability... » read more

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