tag: Mentor

Verification And Test Of Safety And Security
By Brian Bailey - 22 Jun, 2023 - Comments: 0

Functional verification can cost as much as design, but new capabilities are piling onto an already stressed verification methodology, leaving solutions fragmented and incomplete. In a perfect world, a semiconductor device would be verified to operate according to its complete specification, and continue to operate correctly over the course of its useful life. The reality, however, is this i... » read more

Better Choreography Required For Complex Chips
By Karen Heyman - 22 Jun, 2023 - Comments: 0

The rapidly growing number of features and options in chip design are forcing engineering teams to ratchet up their planning around who does what, when it gets done, and how various components will interact. In effect, more elements in the design flow need to be choreographed much more precisely. Some steps have to shift further left, while others need to be considered earlier in the plannin... » read more

Shift Left With Calibre To Optimize IC Design Flow Productivity, Design Quality, And Time To Market
By Siemens EDA - 21 Jun, 2023 - Comments: 0

Every IC designer strives to create a “clean,” or error-free, cell, block, chiplet, SoC, or 3DIC assembly before passing their work downstream for full sign-off verification. However, waiting until sign-off verification to find out how well you did is probably the least efficient approach to achieving production-ready layouts, impacting engineer productivity, project schedules, and hardware... » read more

Blog Review: June 21
By Jesse Allen - 21 Jun, 2023 - Comments: 0

Synopsys' Vikram Bhatia identifies four trends driving the migration of EDA tools and chip design workloads to the cloud, from ever-increasing compute and time-to-market demands to advanced cybersecurity features. Cadence's Veena Parthan checks out how computational fluid dynamics and finite element analysis can help improve aquaculture with sustainable fish cage nets that minimize stagnatio... » read more

Preparing For 5G Millimeter Wave And 6G
By Ed Sperling - 21 Jun, 2023 - Comments: 0

Cellular technology is about to take a giant leap forward, but the packaging, assembly, and testing of the chips used in 5G millimeter wave and the forthcoming 6G ecosystem will be significantly more complicated than anything used in the past. So far, most 5G devices are still working at sub-6 GHz frequencies. A massive rollout of mmWave technology over the next few years will significantly ... » read more

Why Auto Ecosystem Relationships Are Changing
By Ann Mutschler - 19 Jun, 2023 - Comments: 0

The automotive industry is in the midst of rapid change on many fronts. OEMs are exploring new functions and features to add to their vehicles, including chiplets, electrification, autonomous features, as well as new vehicle architectures that will determine how vehicles are going to be designed from the foundation up. But all of this is dependent on the relationships between all of the ecosyst... » read more

Week In Review: Auto, Security, Pervasive Computing
By Liz Allan - 16 Jun, 2023 - Comments: 0

The European Parliament took a major step toward enacting the world’s first laws around the use of AI. Known as the AI Act, the draft law won a majority vote following two years of debate. If the proposed regulations pass the next hurdles, AI systems posing an unacceptable risk to human safety would be banned — along with “intrusive and discriminatory” uses of AI, including biometric su... » read more

Week In Review: Design, Low Power
By Susan Rambo - 16 Jun, 2023 - Comments: 0

Intel released Tunnel Falls, its newest quantum research chip, to quantum computing researchers interested in using the 12-qubit silicon chip for their own experiments and research.  Intel is also providing the chips to research laboratories, with help from LQC (LPS Qubit Collaboratory) through the Army Research Office. The first labs to receive the chip are LPS, Sandia National Laboratories, ... » read more

193i Lithography Takes Center Stage…Again
By Gregory Haley - 15 Jun, 2023 - Comments: 0

Cutting-edge lithography to create smaller features increasingly is being supplemented by improvements in lithography for mature process nodes, both of which are required as SoCs and complex chips are decomposed and integrated into advanced packages. Until the 7nm era, the primary goal of leading-edge chipmakers was to pack everything onto a single system-on-chip (SoC) using the same process... » read more

CEO Outlook: Chiplets, Data Management, And Reliability
By Ed Sperling - 14 Jun, 2023 - Comments: 0

Semiconductor Engineering sat down to talk about changes in chip design with Joseph Sawicki, executive vice president for IC EDA at Siemens Digital Industries Software; John Kibarian, president and CEO of PDF Solutions; John Lee, general manager and vice president of Ansys' Semiconductor Business Unit; Niels Faché, vice president and general manager of PathWave Software Solutions at Keysight; ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy