tag: Mentor

Design For Security Now Essential For Chips, Systems
By Ann Mutschler - 01 Sep, 2022 - Comments: 0

It's nearly impossible to create a completely secure chip or system, but much can be done to raise the level of confidence about that security. In the past, security was something of an afterthought, disconnected from the architecture and added late in the design cycle. But as chips are used increasingly in safety- and mission-critical systems, and as the value of data continues to rise, the... » read more

Enabling Model-Based Design For DO-254 Certification Compliance
By Siemens EDA - 31 Aug, 2022 - Comments: 0

The increasing prevalence and cost of projects that need to comply with the DO-254 standard is forcing companies to evaluate their development processes. This white paper shows a development approach to compliance using model-based design. It covers how a DO-254 workflow using model-based design promotes a consistent requirements-oriented project view and increases reuse of design and verificat... » read more

L5 Adoption Hinges on 5G/6G
By Marie C. Baca - 31 Aug, 2022 - Comments: 1

Truly self-driving cars don’t yet exist, and research shows many consumers are wary of them anyway. What will it take to make fully autonomous cars possible? And how can automakers convince consumers to adopt such vehicles? Experts say the answer to both questions could lie in wireless communication networks. That’s because such networks offer a workaround to a major obstacle in autonomo... » read more

Blog Review: Aug. 31
By Jesse Allen - 31 Aug, 2022 - Comments: 0

Cadence's Paul McLellan wonders what's happened to 450mm wafers as equipment development efforts end, the only wafer fab is decommissioned, and manufacturers see little likelihood to recoup further investment in R&D. Synopsys' Manuel Mota finds that the scale and modular flexibility of chiplets can help meet narrowing time-to-market windows and looks at how UCIe provides a complete stack... » read more

Ensure Functional Safety Using Siemens’ AUTOSAR Solutions
By Siemens EDA - 29 Aug, 2022 - Comments: 0

As the prevalence of automated driving, electrification, and connected vehicle applications increases, the complexity of electrical and electronic (E/E) vehicle architecture is increasing, and vehicle safety requirements are becoming more demanding. Solution architects and engineers are looking for ways to manage it all. And they can, with the help of our comprehensive AUTOSAR solution that pro... » read more

Earlier SoC Design Exploration And Verification Gets Better Designs To Tapeout Faster
By Nermeen Hossam - 25 Aug, 2022 - Comments: 0

By Nermeen Hossam and John Ferguson Between the complexity of advanced node design verification and the competition to be first to the market, system-on-chip (SoC) designers no longer have the luxury of waiting until each sub-block of a chip is DRC-clean to start their chip assembly and verification. Today’s SoC designers typically start chip integration in parallel with block development.... » read more

Verification Scorecard: How Well Is The Industry Doing?
By Brian Bailey - 25 Aug, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss how well verification tools and methodologies have been keeping up with demand, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu Ganguly, vice president of product marketing at Caden... » read more

Is There A Limit To The Number of Layers In 3D-NAND?
By Karen Heyman - 24 Aug, 2022 - Comments: 1

Memory vendors are racing to add more layers to 3D NAND, a competitive market driven by the explosion in data and the need for higher-capacity solid state drives and faster access time. Micron already is filling orders for 232-layer NAND, and not to be outdone, SK Hynix announced that it will begin volume manufacturing 238-layer 512Gb triple level cell (TLC) 4D NAND in the first half of next... » read more

Power Methodology For Estimation And Optimization In The ASIC/SoC Flow
By Siemens EDA - 24 Aug, 2022 - Comments: 0

In this white paper, we’ll review the many steps of today’s common ASIC/SoC power methodologies and tool flows. We’ll then propose ways you can further optimize your power methodology to more quickly achieve your PPW goals. Please note, while we acknowledge that energy consumption in digital CMOS logic is a combination of dynamic power and leakage, to keep this white paper to a digestible... » read more

Blog Review: Aug. 24
By Jesse Allen - 24 Aug, 2022 - Comments: 0

Synopsys' Manuel Mota presents an overview of some of the newest multi-chip module packaging types and their advantages and disadvantages for different kinds of applications, as well as the importance of die-to-die interfaces. Cadence's Steve Brown finds that innovative products require that electronics be analyzed in the context of the environment in which they run, making mechanical and el... » read more

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