tag: methodology

Power Breaks Everything
By Ed Sperling - 15 Jul, 2015 - Comments: 2

The emphasis on lowering power in everything from wearable electronics to data centers is turning into a perfect storm for the semiconductor ecosystem. Existing methodologies need to be fixed, techniques need to be improved, and expectations need to be adjusted. And even then the problems won't go away. In the past, most issues involving power—notably current leakage, physical effects such... » read more

Correct-By-Design Methodology Requires Carefully Defined Constraints
By John McMillan - 14 May, 2015 - Comments: 0

Since the dawn of PCB usage, constraints have been an important part of the design. What are the dimensions? What weight of copper? Now, constraints have become much more than just physical dimensions. The most important constraints are defined by the design requirements of differential pairs, BGAs, low voltage devices, and high-speed parallel interfaces. The cost of rework skyrockets the fu... » read more

IP Design Essentials For Reliability And SoC Integration
By Annapoorna Krishnaswamy - 15 Jan, 2015 - Comments: 0

IP is integral to every SoC design. The need for ubiquitous connectivity has pushed the threshold for content in SoCs even beyond the tenets of Moore’s Law. Technology scaling has not only enabled the delivery of increased performance and reduced power, but also rich content through the integration of a wide range of IPs such as radio devices, CMOS image sensors, MEMs, etc., into a single ... » read more

Is IC Design Methodology At The Breaking Point?
By Randy Smith - 25 Sep, 2014 - Comments: 0

Evidence is mounting that traditional “waterfall” methods used to develop complex ICs are reaching the breaking point. Consider that today: Some IC designs contain more than 100 [getkc id="43" comment="IP"] blocks that must be integrated from multiple sources Design requirements are constantly in flux Demands for low power and security are increasing as device connectivity grows S... » read more

How To Reduce Implementation Headaches In FinFET Processes
By Leah Schuth - 11 Sep, 2014 - Comments: 0

In this era of compressed market windows and shrinking or changing technology, today’s engineers are always looking for ways to improve their overall product performance, power and area (PPA), while also decreasing their SoC design effort. The goal is to ease time-consuming and labor-intensive implementation tasks that will yield a reduction in design time, without sacrificing accuracy and op... » read more

Experts At The Table: The Future Of Verification
By Ed Sperling - 04 Nov, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

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