Navigating the Metrology Maze For GAA FETs


The chip industry is pushing the boundaries of innovation with the evolution of finFETs to gate-all-around (GAA) nanosheet transistors at the 3nm node and beyond, but it also is adding significant new metrology challenges. GAA represents a significant advancement in transistor architecture, where the gate material fully encompasses the nanosheet channel. This approach allows for the vertical... » read more

3D NAND Needs 3D Metrology


By Nick Keller and Andy Antonelli You’ve read the reports: the memory market is floundering as the semiconductor industry moves through another scarcity/surplus cycle. Be that as it may, innovation is happening as the industry continues to pursue increasingly higher three-dimensional stacks, with 3D NAND stacks taller than 200 layers entering production. However, there are challenges... » read more

Demonstrating The Capabilities Of Virtual Wafer Process Modeling And Virtual Metrology


A technical paper titled “Review of virtual wafer process modeling and metrology for advanced technology development” was published by researchers at Coventor Inc., Lam Research. Abstract: "Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the p... » read more

Addressing Copper Clad Laminate Processing Distortion Using Overlay Corrections


All great voyages must come to an end. Such is the case with our series on the challenges facing the manufacturing of advanced IC substrates (AICS), the glue holding the heterogeneous integration ship together. In our first blog, we examined how cumulative overlay drift from individual redistribution layers could significantly increase overall trace length, resulting in higher interconnect res... » read more

Governments Begin To Shape Metrology Directions


Disruptions to the global semiconductor supply chain caused by the COVID-19 pandemic had a severe impact in nearly every sector of the worldwide economy, and especially the worldwide semiconductor market. Due to a shortage of chips, the global auto industry alone suffered a $210 billion loss in 2021, accompanied by a 7.7 million unit production drop, according to AlixPartners, a global consulti... » read more

From Lab To Fab: Increasing Pressure To Fuse IC Processes


Test, metrology, and inspection are essential for both the lab and the fab, but fusing them together so that data created in one is easily transferred to the other is a massive challenge. The chip industry has been striving to bridge these separate worlds for years, but the economics, speed, and complexity of change require a new approach. The never-ending push toward smaller, better-defined... » read more

Full Wafer OCD Metrology


Authored by: Daniel Doutt*a, Ping-ju Chena, Bhargava Ravooria, Tuyen K. Trana, Eitan Rothsteinb, Nir Kampelb, Lilach Tamamb, Effi Aboodyb, Avron Gerb, Harindra Vedalac ABSTRACT Optical Critical Dimension (OCD) spectroscopy is a reliable, non-destructive, and high-throughput measurement technique for metrology and process control that is widely used in semiconductor fabrication facilities (f... » read more

3D Memory Structures: Common Hole And Tilt Metrology Techniques and Capabilities


A technical paper titled "Inline metrology of high aspect ratio hole tilt and center line shift using small-angle x-ray scattering" was published by researchers at Bruker Nano and Lam Research. Abstract: "High aspect ratio (HAR) structures found in three-dimensional nand memory structures have unique process control challenges. The etch used to fabricate channel holes several microns deep... » read more

Reflections On Photomask Japan 2023: Embracing The Era Of Curvilinear Masks


In April, 2023, I had the privilege of participating in Photomask Japan 2023 (PMJ2023), a web conference that brought together experts and enthusiasts in the field. The conference commenced with an enlightening keynote talk by Dr. Kurt Ronse of imec on the status and challenges of the high NA EUV ecosystem, presenting roadmaps for the introduction of high NA EUV. I would like to express my grat... » read more

How Metrology Tools Stack Up In 3D NAND Devices


Multiple innovations in semiconductor processing are needed to enable 3D NAND bit density increases of about 30% per year at ever-decreasing cost per bit, all of which will be required to meet the nonvolatile storage needs of the big data era. 3D NAND is the first truly three-dimensional device in production. It is both a technology driver for new metrology methods and a significant part of ... » read more

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