5 Reasons Why Defect Reduction Is Critical In Semiconductor Material Success

By Jessica Albright - 21 Sep, 2023 - Comments: 0

Semiconductors may be small, but the impacts they have are significant. Semiconductors used in life-dependent applications, such as pacemakers, defibrillators, life support systems, automotive safety systems, or in aviation need to be fail-proof. A device smaller than a centimeter with features just a few nanometers has no margin of error. This blog shares why it’s important to detect materia... » read more

Fab And Field Data Transforming Manufacturing Processes

By Gregory Haley - 12 Sep, 2023 - Comments: 0

The ability to capture, process, and analyze data in the field is transforming semiconductor metrology and testing, providing invaluable insight into a product's performance in real-time and under real-world conditions and use cases. Historically, data that encapsulates parameters such as power consumption, temperature, voltages, currents, timing, and other characteristics, was confined to d... » read more

Navigating the Metrology Maze For GAA FETs

By Gregory Haley - 08 Aug, 2023 - Comments: 1

The chip industry is pushing the boundaries of innovation with the evolution of finFETs to gate-all-around (GAA) nanosheet transistors at the 3nm node and beyond, but it also is adding significant new metrology challenges. GAA represents a significant advancement in transistor architecture, where the gate material fully encompasses the nanosheet channel. This approach allows for the vertical... » read more

3D NAND Needs 3D Metrology

By Nick Keller - 08 Aug, 2023 - Comments: 0

By Nick Keller and Andy Antonelli You’ve read the reports: the memory market is floundering as the semiconductor industry moves through another scarcity/surplus cycle. Be that as it may, innovation is happening as the industry continues to pursue increasingly higher three-dimensional stacks, with 3D NAND stacks taller than 200 layers entering production. However, there are challenges... » read more

Demonstrating The Capabilities Of Virtual Wafer Process Modeling And Virtual Metrology

By Technical Paper Link - 27 Jul, 2023 - Comments: 0

A technical paper titled “Review of virtual wafer process modeling and metrology for advanced technology development” was published by researchers at Coventor Inc., Lam Research. Abstract: "Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the p... » read more

Addressing Copper Clad Laminate Processing Distortion Using Overlay Corrections

By Keith Best - 11 Jul, 2023 - Comments: 0

All great voyages must come to an end. Such is the case with our series on the challenges facing the manufacturing of advanced IC substrates (AICS), the glue holding the heterogeneous integration ship together. In our first blog, we examined how cumulative overlay drift from individual redistribution layers could significantly increase overall trace length, resulting in higher interconnect res... » read more

Governments Begin To Shape Metrology Directions

By Gregory Haley - 11 Jul, 2023 - Comments: 0

Disruptions to the global semiconductor supply chain caused by the COVID-19 pandemic had a severe impact in nearly every sector of the worldwide economy, and especially the worldwide semiconductor market. Due to a shortage of chips, the global auto industry alone suffered a $210 billion loss in 2021, accompanied by a 7.7 million unit production drop, according to AlixPartners, a global consulti... » read more

From Lab To Fab: Increasing Pressure To Fuse IC Processes

By Gregory Haley - 06 Jun, 2023 - Comments: 0

Test, metrology, and inspection are essential for both the lab and the fab, but fusing them together so that data created in one is easily transferred to the other is a massive challenge. The chip industry has been striving to bridge these separate worlds for years, but the economics, speed, and complexity of change require a new approach. The never-ending push toward smaller, better-defined... » read more

Full Wafer OCD Metrology

By Nova - 06 Jun, 2023 - Comments: 0

Authored by: Daniel Doutt*a, Ping-ju Chena, Bhargava Ravooria, Tuyen K. Trana, Eitan Rothsteinb, Nir Kampelb, Lilach Tamamb, Effi Aboodyb, Avron Gerb, Harindra Vedalac ABSTRACT Optical Critical Dimension (OCD) spectroscopy is a reliable, non-destructive, and high-throughput measurement technique for metrology and process control that is widely used in semiconductor fabrication facilities (f... » read more

3D Memory Structures: Common Hole And Tilt Metrology Techniques and Capabilities

By Technical Paper Link - 03 Jun, 2023 - Comments: 0

A technical paper titled "Inline metrology of high aspect ratio hole tilt and center line shift using small-angle x-ray scattering" was published by researchers at Bruker Nano and Lam Research. Abstract: "High aspect ratio (HAR) structures found in three-dimensional nand memory structures have unique process control challenges. The etch used to fabricate channel holes several microns deep... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: metrology