Chip Industry Week In Review


Samsung unveiled its latest 2nm and 4nm process nodes, plus its AI solutions during the Samsung Foundry Forum. The company also introduced an aggressive roadmap for the next few years that includes 3D-ICs with logic-on-logic, starting in 2025; custom HBM with built-in logic; backside power delivery on 2nm technology in 2027; and co-packaged optics. In presentations at the event, the company als... » read more

Chip Industry Week In Review


President Biden announced four new Workforce Hubs to support the CHIPS Act and other initiatives, in Upstate New York, Michigan, Milwaukee, and Philadelphia. The White House also provided economic context and progress updates for the President’s workforce strategy. Samsung began mass production of its ninth-gen industry-first V-NAND chip. Along with one-terabit triple-level cell design, th... » read more

Chip Industry Week In Review


By Jesse Allen, Susan Rambo, and Liz Allan The U.S. government will invest about $3 billion for the National Advanced Packaging Manufacturing Program (NAPMP), including an advanced packaging piloting facility to help U.S. manufacturers adopt new technology and workforce training programs. It also will provide funding for projects concentrating on materials and substrates; equipment, tools, ... » read more

Technical Paper Roundup: Sept 11


New technical papers added to Semiconductor Engineering’s library this week. [table id=136 /] (more…) » read more

The Utility Of Shallow Dynamic Circuits For Long-Range Entanglement On Large-Scale Quantum Devices


A technical paper titled “Efficient Long-Range Entanglement using Dynamic Circuits” was published by researchers at IBM Research, IBM T.J. Watson Research Center, University of Southern California, MIT-IBM Watson AI Lab, and IBM Quantum. Abstract: "Quantum simulation traditionally relies on unitary dynamics, inherently imposing efficiency constraints on the generation of intricate entangl... » read more

Technical Paper Roundup: Sept 5


New technical papers added to Semiconductor Engineering’s library this week. [table id=132 /] (more…) » read more

How A Fault-Tolerant Quantum Memory Could Be Realized Using Near-Term Quantum Processors With Small Qubit Overhead


A technical paper titled “High-threshold and low-overhead fault-tolerant quantum memory” was published by researchers at IBM T.J. Watson Research Center and MIT-IBM Watson AI Lab. Abstract: "Quantum error correction becomes a practical possibility only if the physical error rate is below a threshold value that depends on a particular quantum code, syndrome measurement circuit, and a decod... » read more

Chip Industry’s Technical Paper Roundup: Feb. 14


New technical papers recently added to Semiconductor Engineering’s library: [table id=80 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us p... » read more

New Method Improves Machine Learning Models’ Reliability, With Less Computing Resources (MIT, U. of Florida, IBM Watson)


A new technical paper titled "Post-hoc Uncertainty Learning using a Dirichlet Meta-Model" was published (preprint) by researchers at MIT, University of Florida, and MIT-IBM Watson AI Lab (IBM Research). The work demonstrates how to quantify the level of certainty in its predictions, while using less compute resources. “Uncertainty quantification is essential for both developers and users o... » read more