tag: modeling

Radar Systems
By Cadence - 05 Jan, 2022 - Comments: 0

Combined with advances in phased-array antennas and integration technologies, radars are moving beyond military/aerospace markets to address a host of commercial applications. This white paper showcases how the Cadence AWR Design Environment platform provides designers with a host of modeling and simulation technologies needed to meet the challenges of all types of radar system design. Click h... » read more

Structural Vs. Functional
By Brian Bailey - 23 Nov, 2021 - Comments: 0

When working on an article about PLM and semiconductors, I got to review a favorite topic from my days in EDA development – verification versus validation. I built extensive presentations around it and tried to persuade people within the EDA industry, as well as customers, about the advantages of doing a top-down functional modeling and analysis. The V diagram that everyone uses is flawed and... » read more

Materials and Device Simulations for Silicon Qubit Design and Optimization
By Technical Paper Link - 27 Oct, 2021 - Comments: 0

Abstract: "Silicon-based microelectronics technology is extremely mature, yet this profoundly important material is now also poised to become a foundation for quantum information processing technologies. In this article, we review the properties of silicon that have made it the material of choice for semiconductor-based qubits with an emphasis on the role that modeling and simulation have play... » read more

Modeling electrical conduction in resistive-switching memory through machine learning
By Technical Paper Link - 04 Oct, 2021 - Comments: 0

Published in AIP Advances on July 13, 2021. Read the full paper (open access). Abstract Traditional physical-based models have generally been used to model the resistive-switching behavior of resistive-switching memory (RSM). Recently, vacancy-based conduction-filament (CF) growth models have been used to model device characteristics of a wide range of RSM devices. However, few have focused o... » read more

CEO Outlook: More Data, More Integration, Same Deadlines
By Ed Sperling - 24 Jun, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the future of chip design and EDA tools with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; and Babak Taheri, CEO of Silvaco. What ... » read more

Standards, Open Source, and Tools
By Brian Bailey - 10 May, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering discussed what open source verification means today and what it should evolve into with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Ashish Darbari, CEO of Axiomise; Simon Davidmann, CEO of Imperas Software; Serge Leef, program manager in the Microsystems Technology Office at DARPA; Tao Liu, staff hardware engineer... » read more

The Advantages Of MBSE-Driven E/E Architecture
By Mentor, a Siemens Business - 07 Oct, 2020 - Comments: 0

Vehicles in all sectors are growing in complexity as OEMs develop sophisticated platforms with growing levels of automation and connectivity. To cope with this growing complexity, automotive, aerospace and commercial vehicle OEMs must evolve their architectural design processes to leverage MBSE and the digital thread. Today’s E/E system engineering solutions help companies implement MBSE by p... » read more

Preparing For A Barrage Of Physical Effects
By Ann Mutschler - 13 Aug, 2020 - Comments: 0

Advancements in 3D transistors and packaging continue to enable better power and performance in a given footprint, but they also require more attention to physical effects stemming from both increased density and vertical stacking. Even in planar chips developed at 3nm, it will be more difficult to build both thin and thick oxide devices, which will have an impact on everything from power to... » read more

The Evolution Of Digital Twins
By Brian Bailey - 03 Aug, 2020 - Comments: 1

Digital twins are starting to make inroads earlier in the chip design flow, allowing design teams to develop more effective models. But they also are adding new challenges in maintaining those models throughout a chip's lifecycle. Until a couple of years ago, few people in the semiconductor industry had even heard the term "digital twin." Then, suddenly, it was everywhere, causing confusion ... » read more

Wrestling With Variation In Advanced Node Designs
By Ann Mutschler - 19 Feb, 2020 - Comments: 5

Variation is becoming a major headache at advanced nodes, and issues that used to be dealt with in the fab now must be dealt with on the design side, as well. What is fundamentally changing is that margin, which has long been used as a buffer for variation and other manufacturing process-related problems, no longer works in these leading-edge designs for a couple of reasons. First, margin im... » read more

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