tag: modeling

Timing Is Of The Essence
By Ansys - 14 Mar, 2019 - Comments: 0

Today's advanced 16/7nm system-on-chips (SoCs) are faced with increased variation as they push for lower power. While the sizes of the transistors continue to shrink following Moore's Law, the threshold voltages fail to scale. This causes wide timing variability leading to timing closure difficulties, design re-spins and poor functional yield. Learn how ANSYS Path FX with its unique variatio... » read more

Edge Inferencing Challenges
By Ed Sperling - 10 Jan, 2019 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks about balancing different variables to improve performance and reduce power at the lowest cost possible in order to do inferencing in edge devices. https://youtu.be/1BTxwew--5U » read more

Electromagnetic Analysis and Signoff: Cost Savings
By Magdy Abadir - 18 Sep, 2018 - Comments: 0

By Nikolas Provatas and Magdy Abadir We are often asked by SoC design teams about the benefits of an electromagnetic analysis and signoff methodology. Here is an overview of some of the big “cost savings”. Time to Market Savings Utilizing an EM crosstalk analysis and signoff methodology provides designers with an “insurance policy” against the risk of EM coupling in their SOC des... » read more

Process Corner Explosion
By Ann Mutschler - 13 Sep, 2018 - Comments: 1

The number of corners that need to be checked is exploding at 7nm and below, fueled by everything from temperature and voltage to changes in metal. Lowering risk and increasing predictability of an SoC at those nodes starts with understanding what will happen when a design is manufactured on a particular foundry process, captured in process corners. This is basically a way of modeling what i... » read more

Design Reuse Vs. Abstraction
By Ann Mutschler - 05 Jul, 2018 - Comments: 1

Chip designers have been constantly searching for a hardware description language abstraction level higher than RTL for a few decades. But not everyone is moving in that direction, and there appear to be enough options available through design reuse to forestall that shift for many chipmakers. Pushing to new levels of abstraction is frequent topic of discussion in the design world, particula... » read more

Searching For A System Abstraction
By Brian Bailey - 28 Jun, 2018 - Comments: 3

Without abstraction, advances in semiconductor design would have stalled decades ago and circuits would remain about the same size as analog blocks. No new abstractions have emerged since the 1990s that have found widespread adoption. The slack was taken up by IP and reuse, but IP blocks are becoming larger and more complex. Verification by isolation is no longer a viable strategy at the system... » read more

Backchannel Modeling And Simulation Using Recent Enhancements To The IBIS Standard
By Cadence - 23 May, 2018 - Comments: 0

Recent enhancements to the upcoming IBIS standard now support backchannel training, enabling IBIS-AMI models to emulate this real-world SerDes behavior. AMI modelers now can incorporate backchannel algorithms into their IBIS-AMI models, automating the optimization of transmitter and receiver equalization settings in the same manner as their actual SerDes hardware devices. This saves system desi... » read more

Merging Verification With Validation
By Brian Bailey - 22 Mar, 2018 - Comments: 3

Verification and validation are two important steps in the creations of electronic systems and over time their roles, but how they play together is changing. In fact, today we are seeing a major opportunity for rethinking this aspect of the flow, which could mean the end of them as separate tasks for many of the chips being created. As with many things in this industry, however, squeezing it... » read more

Tech Talk: 5/3nm Parasitics
By Ed Sperling - 22 Feb, 2018 - Comments: 0

Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs. https://youtu.be/24C6byQBkuI » read more

Signal Integrity Methodology For Double-Digit Multi-Gigabit Interfaces
By Cadence - 07 Feb, 2018 - Comments: 0

As data rates for serial link interfaces such as PCI Express (PCIe) Gen 4 move into the double digits, device modeling, interconnect modeling, and analysis methodologies must continue to evolve to address the shrinking design margins and increasingly challenging compliance criteria facing today’s engineers. To mitigate risk and optimize designs, it is critical to move analysis as far upstream... » read more

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