tag: modeling

Changes In AI SoCs
By Ed Sperling - 12 Feb, 2020 - Comments: 0

Kurt Shuler, vice president of marketing at ArterisIP, talks about the tradeoffs in AI SoCs, which range from power and performance to flexibility, depending on whether processing elements are highly specific or more general, and the need for more modeling of both hardware and software together. » read more

Distributed Design Implementation
By Ed Sperling - 04 Dec, 2019 - Comments: 0

PV Srinivas, group director for R&D at Synopsys, talks about the impact of larger chips and increasing complexity on design productivity, why divide-and-conquer doesn’t work so well anymore, and how to reduce the number of blocks that need to be considered to achieve faster timing closure and quicker time to market. » read more

Ensuring A 5G Design Is Viable
By Ed Sperling - 09 Sep, 2019 - Comments: 0

Ron Squiers, network solutions specialist at Mentor, a Siemens Business, explains what’s different in 5G chips versus 4G, how to construct a front haul and back haul system so it is testable in the network stack. » read more

Digital Twins Deciphered
By Brian Bailey - 28 Mar, 2019 - Comments: 0

Ever since Siemens acquired Mentor Graphics in 2016, a new phrase has become more common in the semiconductor industry – the digital twin. Exactly what that is, and what impact it will have on the semiconductor industry, is less clear. In fact, many in the industry are scratching their heads over the term. The initial reaction is that the industry has been creating what are now termed digi... » read more

Timing Is Of The Essence
By Ansys - 14 Mar, 2019 - Comments: 0

Today's advanced 16/7nm system-on-chips (SoCs) are faced with increased variation as they push for lower power. While the sizes of the transistors continue to shrink following Moore's Law, the threshold voltages fail to scale. This causes wide timing variability leading to timing closure difficulties, design re-spins and poor functional yield. Learn how ANSYS Path FX with its unique variatio... » read more

Edge Inferencing Challenges
By Ed Sperling - 10 Jan, 2019 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks about balancing different variables to improve performance and reduce power at the lowest cost possible in order to do inferencing in edge devices. https://youtu.be/1BTxwew--5U » read more

Electromagnetic Analysis and Signoff: Cost Savings
By Magdy Abadir - 18 Sep, 2018 - Comments: 0

By Nikolas Provatas and Magdy Abadir We are often asked by SoC design teams about the benefits of an electromagnetic analysis and signoff methodology. Here is an overview of some of the big “cost savings”. Time to Market Savings Utilizing an EM crosstalk analysis and signoff methodology provides designers with an “insurance policy” against the risk of EM coupling in their SOC des... » read more

Process Corner Explosion
By Ann Mutschler - 13 Sep, 2018 - Comments: 1

The number of corners that need to be checked is exploding at 7nm and below, fueled by everything from temperature and voltage to changes in metal. Lowering risk and increasing predictability of an SoC at those nodes starts with understanding what will happen when a design is manufactured on a particular foundry process, captured in process corners. This is basically a way of modeling what i... » read more

Design Reuse Vs. Abstraction
By Ann Mutschler - 05 Jul, 2018 - Comments: 1

Chip designers have been constantly searching for a hardware description language abstraction level higher than RTL for a few decades. But not everyone is moving in that direction, and there appear to be enough options available through design reuse to forestall that shift for many chipmakers. Pushing to new levels of abstraction is frequent topic of discussion in the design world, particula... » read more

Searching For A System Abstraction
By Brian Bailey - 28 Jun, 2018 - Comments: 3

Without abstraction, advances in semiconductor design would have stalled decades ago and circuits would remain about the same size as analog blocks. No new abstractions have emerged since the 1990s that have found widespread adoption. The slack was taken up by IP and reuse, but IP blocks are becoming larger and more complex. Verification by isolation is no longer a viable strategy at the system... » read more

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