Reasons To Know IGZO

By Katherine Derbyshire - 15 Aug, 2024 - Comments: 0

Interest in monolithic 3D integration is driven by both compute-in-memory applications and a more general need for increased circuit density. Compute-in-memory architectures seek to reduce the power requirements of machine learning workloads, which are dominated by the movement of data between memory and logic components. Even in conventional architectures, though, placing high-density, high-ba... » read more

Building CFETs With Monolithic And Sequential 3D

By Katherine Derbyshire - 22 Feb, 2024 - Comments: 0

Successive versions of vertical transistors are emerging as the likely successor to finFETs, combining lower leakage with significant area reduction. A stacked nanosheet transistor, introduced at N3, uses multiple channel layers to maintain the overall channel length and necessary drive current while continuing to reduce the standard cell footprint. The follow-on technology, the CFET, pushes... » read more

3D-IC Design Challenges And Requirements

By Cadence - 27 Oct, 2021 - Comments: 0

As demands accelerate for increasing density, higher bandwidths, and lower power, many IC design and packaging teams are taking a close look at vertical stacking multiple chips and chiplets. This technology, called 3D-IC, promises many advantages over traditional single-die planar designs. Some are using the term “More-than-Moore” to describe the potential of this new technology. Integratio... » read more

Momentum Builds For Monolithic 3D ICs

By Mark LaPedus - 14 Nov, 2013 - Comments: 1

The 2.5D/3D chip market is heating up on several fronts. On one front, stacked-die using through-silicon vias (TSVs) is taking root. In a separate area, Samsung is sampling the world’s first 3D NAND device, with Micron and SK Hynix expected to follow suit. And now, there is another technology generating steam—monolithic 3D integrated circuits. In stacked-die, bare die are connected using... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: monolithic 3D integration

Reasons To Know IGZO

Building CFETs With Monolithic And Sequential 3D

3D-IC Design Challenges And Requirements

Momentum Builds For Monolithic 3D ICs