tag: Moortec

Is DVFS Worth The Effort?
By Brian Bailey - 10 Sep, 2020 - Comments: 2

Almost all designs have become power-aware and are being forced to consider every power saving technique, but not all of them are yielding the expected results. Moreover, they can add significant complexity into designs, increasing the time it takes to get to tapeout and boosting up the cost. Dynamic voltage and frequency scaling (DVFS) is one such power and energy saving technique now being... » read more

A Historical Case For Precision
By Lee Vick - 10 Sep, 2020 - Comments: 0

We take for granted today the staggering precision of modern technology. Cars, electronics, robots, and medical equipment all come off the factory floor composed of effortlessly interchangeable parts, but this was not always the case. In the late 18th century most things that required any kind of precision were made by hand, one notable example being the flintlock musket. You see, back then if ... » read more

Dealing With Device Aging At Advanced Nodes
By Ann Mutschler - 10 Sep, 2020 - Comments: 0

Premature aging of circuits is becoming troublesome at advanced nodes, where it increasingly is complicated by new market demands, more stress from heat, and tighter tolerances due to increased density and thinner dielectrics. In the past, aging and stress largely were separate challenges. Those lines are starting to blur for a number of reasons. Among them: In automotive, advanced-node... » read more

Week In Review: Design, Low Power
By Jesse Allen - 21 Aug, 2020 - Comments: 0

Tools & IP SiFive announced OpenFive, a self-contained and autonomous business unit that will offer custom silicon solutions with differentiated IP. OpenFive will be led by Dr. Shafy Eltoukhy, SVP, and general manager of OpenFive. OpenFive debuted with a new Die-to-Die (D2D) interface IP portfolio to serve next-generation chipset based designs for networking, HPC, and AI markets. The D2D p... » read more

Monitoring Chips After Manufacturing
By Brian Bailey - 19 Aug, 2020 - Comments: 2

New regulations and variability of advanced process nodes are forcing chip designers to insert additional capabilities in silicon to help with comprehension, debug, analytics, safety, security, and design optimization. The impact of this will be far-reaching as the industry discusses what capabilities can be shared between these divergent tasks, the amount of silicon area to dedicate to it, ... » read more

Redefining The Power Delivery Network
By Brian Bailey - 13 Aug, 2020 - Comments: 3

Reliably getting power around a package containing multiple dies, potentially coming from multiple sources, or implemented in diverse technologies, is becoming much more difficult. The tools and needed to do this in an optimized manner are not all there today. Nevertheless, the industry is confident that we can get there. For a single die, the problem has evolved slowly over time. "For a ... » read more

Managing Worst Case Power Conditions
By Richard McPartland - 13 Aug, 2020 - Comments: 0

With each new technology node, especially FinFET, the dynamic conditions within a chip are changing and becoming more complex in terms of process speeds, thermal activity and supply variation. Dennard scaling brought about the ability for power to be scaled down with each successive node so that power per unit area stayed roughly constant. However, as highlighted by John Hennessy at last y... » read more

Power And Performance Optimization At 7/5/3nm
By Ed Sperling - 13 Aug, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at Synopsys; Bryan Bowyer, director of engineering at Mentor, a Siemens Business; Kiran Burli, senior director of marketing for Arm's Physical Design Group; Kam Kittrell, senior product management group d... » read more

Blog Review: Aug. 12
By Jesse Allen - 12 Aug, 2020 - Comments: 0

Arm's Greg Yeric takes a look at what semiconductor manufacturing might look like in 2030 as the price of equipment rises and possibilities for when the next upgrade to EUV, high numerical aperture, eventually runs out of steam. Synopsys' Taylor Armerding explains the difference between bugs and security flaws and why it's so important to pay attention to potential problems in a design's spe... » read more

Ins And Outs Of In-Circuit Monitoring
By Ed Sperling - 21 Jul, 2020 - Comments: 2

At 7nm and 5nm, in-circuit monitoring is becoming essential. Steve Crosher, CEO of Moortec, talks about the impact of rising complexity, how different use cases and implementations can affect reliability and uptime, and why measuring electrical, voltage and thermal stress can be used to statistically predict failures and improve reliability throughout a chip’s lifetime. » read more

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