Managing Voltage Variation

By Barry Pangrle - 07 Aug, 2023 - Comments: 0

Engineers make many tradeoffs when designing SoC’s to better meet design specifications. Power, Performance and Area (PPA) are the primary goals and all three impact the cost of the implementation. For example, higher power and performance can both require more expensive packaging for power and signal integrity as well as cooling. The larger the die area the fewer die per wafer which drives u... » read more

Battling Over Shrinking Physical Margin In Chips

By Ed Sperling - 31 Jul, 2023 - Comments: 0

Smaller process nodes, coupled with a continual quest to add more features into designs, are forcing chipmakers and systems companies to choose which design and manufacturing groups have access to a shrinking pool of technology margin. In the past margin largely was split between the foundries, which imposed highly restrictive design rules (RDRs) to compensate for uncertainties in new proces... » read more

Synchronous Die-to-Die Signaling Using Aeonic Connect

By Movellus - 26 Jul, 2023 - Comments: 0

This paper presents a system providing accurate clock alignment for on-die and die-to-die synchronous circuits. A low-frequency reference clock provides an accurate timing reference with low power consumption, while distributed delay lines align the endpoints of loosely constrained clock trees. For on-die clocks, this synchronization strategy severs the traditional relationship between power an... » read more

Demand For Timing Innovation Grows

By Jeff Goldman - 19 Jul, 2023 - Comments: 0

The semiconductor industry has begun exploring a range of timing options as demand for increased performance and more features exceeds the ability to design chips using the same techniques and technology that have been relied on for decades. Like many elements in computing, timing is a hierarchy or stack. It includes everything from partitioning AI computations into multiple parts and assemb... » read more

Supercomputing Efficiency Lags Performance Gains

By Barry Pangrle - 30 Jun, 2023 - Comments: 0

In last month’s article, Top 500: Frontier is Still on Top, I wrote about the latest versions of the Top500 and Green500 lists. Power is an incredibly important aspect of designing a world performance leading supercomputer. (Why, I can remember back to when you could run the world’s fastest machine on only a couple MW of power.) The first Green500 list was published back in 2013. Happy 1... » read more

Week In Review: Design, Low Power

By Susan Rambo - 16 Jun, 2023 - Comments: 0

Intel released Tunnel Falls, its newest quantum research chip, to quantum computing researchers interested in using the 12-qubit silicon chip for their own experiments and research. Intel is also providing the chips to research laboratories, with help from LQC (LPS Qubit Collaboratory) through the Army Research Office. The first labs to receive the chip are LPS, Sandia National Laboratories, ... » read more

Mitigating Voltage Droop

By Aakash Jani - 13 Jun, 2023 - Comments: 0

Voltage droop, also known as IR drop, is a phenomenon that occurs when the current in the power delivery network abruptly changes due to workload fluctuations. This can lead to supply voltage drops across system-on-chips (SoCs) which can cause severe performance degradation, limit their energy efficiency, and in extreme cases can cause catastrophic timing failures. To avoid these issues, conven... » read more

Top500: Frontier Is Still On Top

By Barry Pangrle - 25 May, 2023 - Comments: 0

The latest versions of the Top500 and Green500 lists were just released on May 22, 2023. The last time that I wrote about the Green500, a Chinese machine, NRCPC’s Sunway TaihuLight, was sitting at the top of the Top500 list. It’s been a while since I last wrote about these lists and it’s interesting to look back at the leap in performance and energy efficiency over the past 7 years. ... » read more

TSMC Targets N2 Production For 2025

By Barry Pangrle - 02 May, 2023 - Comments: 0

April ended with TSMC’s financial results for the 1st Quarter of 2023 reported on April 20, 2023, and their North American Technology Symposium was held on April 27 at the Santa Clara Convention Center. TSMC’s N3 entered volume production in 4Q 2022 and TSMC’s N2 “nanosheet” technology is on schedule for production in 2025. TSMC’s CEO, C.C. Wei, said during the 1Q conference cal... » read more

Squeezing The Margins

By Barry Pangrle - 29 Mar, 2023 - Comments: 0

Back in 2016, we looked at the MediaTek Helio X20, the first Tri-Gear mobile SoC. Tri-Gear is a step beyond ARM’s big.LITTLE concept of using two different cores that have unique power and performance characteristics, by adding a third core. The main advantage to this approach is having more core choices to best run workloads at better energy efficiency and performance operating points. At... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

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