Research Bits: Oct. 7


Doping oxide insulator improves SiGe conductivity Researchers from TU Wien, Johannes Kepler University Linz, and TU Bergakademie Freiberg manufactured a silicon-germanium (SiGe) transistor using an alternative approach that involves doping the insulating oxide layer to produce a long-range effect that extends into the semiconductor. Called modulation acceptor doping (MAD), the technique ena... » read more

Chip Industry Technical Paper Roundup: Sept 16


New technical papers recently added to Semiconductor Engineering’s library: [table id=477 /] Find more semiconductor research papers here. » read more

Critical Challenges and Opportunities Related to Polymer-Based Materials in Semiconductor Packaging (NIST, NC State, NREL et al)


A new technical paper titled "Material Needs and Measurement Challenges for Advanced Semiconductor Packaging: Understanding the Soft Side of Science" was published by researchers at the National Institute of Standards and Technology, North Carolina State University, National Renewable Energy Laboratory, ASE, Intel, Innocentrix, and Binghamton University. Abstract "This Perspective builds up... » read more

Research Bits: Mar. 25


2D materials in 3D transistors Researchers at the University of California Santa Barbara investigated 3D gate-all-around (GAA) transistors made using 2D semiconductors. They considered three different approaches to channel stacking: nano-sheet FETs, nano-fork FETs, and nano-plate FETs. The nano-plate FET architecture, which exploits lateral stacking of 2D layers, was found to maximize the g... » read more

Chip Industry Technical Paper Roundup: Dec. 23


New technical papers recently added to Semiconductor Engineering’s library: [table id=394 /] Find all technical papers here. » read more

Patterning Doping On Very Large Monolayer MoS2 (NREL)


A new technical paper titled "Spatially Precise Light-Activated Dedoping in Wafer-Scale MoS2 Films" was published by researchers at National Renewable Energy Laboratory (NREL) and Renewable & Sustainable Energy Institute (RASEI). "In this work, we unravel the mechanism that drives PL* changes of MoS2 monolayers under laser illumination in ambient conditions. We demonstrate the critical ... » read more

Chip Industry Technical Paper Roundup: July 30


New technical papers recently added to Semiconductor Engineering’s library, including a best paper award winner at ISCA. [table id=246 /] More ReadingTechnical Paper Library home » read more

Ultrafast Charge Transfer Cascade In Semiconductor Materials


A technical paper titled “Ultrafast Charge Transfer Cascade in a Mixed-Dimensionality Nanoscale Trilayer” was published by researchers at the National Renewable Energy Laboratory. Abstract: "Innovation in optoelectronic semiconductor devices is driven by a fundamental understanding of how to move charges and/or excitons (electron-hole pairs) in specified directions for doing useful work, ... » read more

Chip Industry Week In Review


By Adam Kovac, Gregory Haley, and Liz Allan. The U.S. government released a 61-page report, titled "National Strategy on Microelectronics Research,” by the Subcommittee On Microelectronics Leadership. It provides a framework for government, industry, academia, and international allies to address four major goals. Synopsys  acquired Intrinsic ID, which develops physical unclonable func... » read more

Week In Review: Design, Low Power


Deals Utilidata and Nvidia are teaming up on a software-defined smart grid chip that can be embedded in smart meters to with the aim of improving grid resiliency and integrating distributed energy resources (DERs) such as solar, storage, and electric vehicles. The U.S. Department of Energy’s National Renewable Energy Laboratory (NREL) will test the software-defined smart grid chip as a way t... » read more

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