tag: NoC

Cache Coherence In Network On Chip Design (NTU)
By Technical Paper Link - 08 Apr, 2025 - Comments: 0

A new technical paper titled "Learning Cache Coherence Traffic for NoC Routing Design" was published by researchers at Nanyang Technological University. "In this work, we propose a cache coherence-aware routing approach with integrated topology selection, guided by our Cache Coherence Traffic Analyzer (CCTA). Our method achieves up to 10.52% lower packet latency, 55.51% faster execution time... » read more

Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs
By Andy Nightingale - 27 Mar, 2025 - Comments: 0

In system-on-chip (SoC) design, wire length refers to the total physical distance of interconnects within a network-on-chip (NoC). It is a critical parameter that influences performance, power consumption, and manufacturing costs. Today’s SoCs incorporate numerous IP blocks connected by multiple complex NoCs and require efficient management of wire lengths. Excessive wire length increases lat... » read more

Accelerate And Derisk RISC-V- Based SoC Designs
By Arteris - 26 Mar, 2025 - Comments: 0

How to accelerate and derisk RISC-V-based SoC designs using silicon-proven network-on-chip IP and SoC integration automation software. This technology seamlessly connects any IP from multiple vendors and shortens design cycles and time to revenue. Maximize overall efficiency for the best product design, leveraging the best NoC IP and expert support. Read more here. » read more

Optimizing Data Movement In SoCs And Advanced Packages
By Ed Sperling - 18 Mar, 2025 - Comments: 0

The amount of data that needs to move around a chip is growing exponentially, driven by the rollout of AI and more sensors everywhere. There may be hundreds of IP blocks, more compute elements, and many more wires to contend with. Andy Nightingale, vice president of product management and marketing at Arteris, talks about the demand for low-latency on-chip communication in increasingly complex ... » read more

Top 5 Reasons Engineers Need A Smart NoC
By Rick Bye - 27 Feb, 2025 - Comments: 0

As system-on-chip (SoC) designs grow more complex, IP interconnect engineers struggle with achieving optimal scalability, performance, and power efficiency. The increasing number of IP blocks, often ranging from 50 to more than 500, introduces significant interconnect congestion, timing closure issues, and power dissipation challenges. Additionally, many network-on-chip (NoC) design tasks are s... » read more

Boost SoC Efficiency And Speed With FlexGen Smart NoC IP Automation
By Arteris - 26 Feb, 2025 - Comments: 0

Today’s high-end SoCs contain many heterogeneous processing elements to address the needs of HPC and AI applications. These include Central Processing Units (CPUs), Graphics Processing Units (GPUs), Neural Processing Units (NPUs), Tensor Processing Units (TPUs), and other hardware accelerators. Furthermore, IPs may contain clusters of these processor cores, and SoC subsystems may include arra... » read more

From DIY To Advanced NoC Solutions: The Future Of MCU Design
By Andy Nightingale - 30 Jan, 2025 - Comments: 0

The evolution of microcontrollers (MCUs) has significantly transformed embedded systems, shifting from simple, standalone processors to complex, multifunctional units that rival traditional systems-on-chip (SoCs). These advancements are fueled by the demand for increased computational efficiency, cutting-edge features like AI and machine learning (ML) integration, and the need to address growin... » read more

2024 Set The Stage For NoC Interconnect Innovations In SoC Design
By Andy Nightingale - 19 Dec, 2024 - Comments: 0

What a year it’s been for Arteris! Reflecting on 2024, the company achieved exciting milestones and breakthroughs that pushed the boundaries of system-on-chip (SoC) design. A game-changing new technology was unveiled, a major product was launched, and existing solutions were tailored for AI, automotive, high-performance computing (HPC) and more. Along the way, we welcomed new partners and ... » read more

Scaling AI Chip Design With NoC Soft Tiling
By Andy Nightingale - 26 Nov, 2024 - Comments: 0

Tiling is about repeating modular units within the same chip to enhance scalability and efficiency; chiplets involve combining different silicon pieces to achieve a more diverse and powerful system within a single package. Network-on-chip (NoC) soft tiling is complimentary but distinct from chiplets described above as it repeats modular units inside a NoC design. Soft tiling within a NoC off... » read more

RISC-V’s Software Portability Challenge
By Brian Bailey - 13 Nov, 2024 - Comments: 0

Experts At The Table: RISC-V provides a platform for customization, but verifying those changes remains challenging. Semiconductor Engineering discussed the issue with John Min, vice president of customer service at Arteris; Zdeněk Přikryl, CTO of Codasip; Neil Hand, director of marketing at Siemens EDA (at the time of this discussion); Frank Schirrmeister, executive director for strategi... » read more

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