tag: NoC

OTA On-Chip Computing That Conquers A Bottleneck In Wired NoC Architectures
By Technical Paper Link - 21 Jun, 2022 - Comments: 0

New research paper titled "Wireless On-Chip Communications for Scalable In-memory Hyperdimensional Computing" from researchers at IBM Research, Zurich Switzerland and Universitat Politecnica de Catalunya, Barcelona, Spain Abstract: "Hyperdimensional computing (HDC) is an emerging computing paradigm that represents, manipulates, and communicates data using very long random vectors (aka hyp... » read more

Deep Reinforcement Learning to Dynamically Configure NoC Resources
By Technical Paper Link - 17 Jun, 2022 - Comments: 0

New research paper titled "Deep Reinforcement Learning Enabled Self-Configurable Networks-on-Chip for High-Performance and Energy-Efficient Computing Systems" from Md Farhadur Reza at Eastern Illinois University. Find the open access technical paper here. Published June 2022. M. F. Reza, "Deep Reinforcement Learning Enabled Self-Configurable Networks-on-Chip for High-Performance and Energ... » read more

IP Industry Transformation
By Brian Bailey - 09 Jun, 2022 - Comments: 0

The design IP industry is developing an assortment of new options and licensing schemes that could affect everything from how semiconductor companies collaborate to how ICs are designed, packaged, and brought to market. The IP market already has witnessed a sweeping shift from a "design once, use everywhere" approach, to an "architect once, customize everywhere" model, in which IP is highly ... » read more

Optimizing NoC-Based Designs
By Paul Graykowski - 05 May, 2022 - Comments: 0

Semiconductor development is currently in a phase of rapid evolution driven by the combination of new technologies and methodologies. The technique of combining multiple functions into systems-on-chips (SoCs) is continuing to grow in complexity. Rapid advancement in new technologies for market segments like data centers, robotics, ADAS and artificial intelligence/machine learning (AI/ML) are re... » read more

Adaptive Scheduling for Time-Triggered Network-on-Chip-Based Multi-Core Architecture Using Genetic Algorithm
By Technical Paper Link - 10 Jan, 2022 - Comments: 0

Abstract "Adaptation in time-triggered systems can be motivated by energy efficiency, fault recovery, and changing environmental conditions. Adaptation in time-triggered systems is achieved by preserving temporal predictability through metascheduling techniques. Nevertheless, utilising existing metascheduling schemes for time-triggered network-on-chip architectures poses design time computatio... » read more

End-To-End Traceability
By Ed Sperling - 29 Nov, 2021 - Comments: 0

Despite standards such as ISO 26262 and IEC 61508, there are still disconnects and gaps in the supply chain and design-through-manufacturing flows. Kurt Shuler, vice president of marketing at Arteris IP, digs into what's missing, why changes made in one area are not reflected in other areas and throughout the product lifecycle, and why various different phases of the flow don't always match up ... » read more

Reviving The IPO Route For IP Companies
By Ed Sperling - 01 Nov, 2021 - Comments: 0

K. Charles Janac, chairman and CEO of Arteris IP, sat down with Semiconductor Engineering to talk about the company's recent decision to go public, including the benefits and risks of operating as a public IP company. SE: The rule of thumb used to be $20 million in revenue was needed for an IP company to do an IPO at the turn of the Millennium, and then it increased to $40 million about a de... » read more

More NoC Wisdom
By Kurt Shuler - 07 Oct, 2021 - Comments: 0

A common experience for anyone promoting a disruptive technology is that prospective customers understand that what is being offered is different. Still, without a familiar reference to compare, they extrapolate expectations unreliably. Sometimes expectations are extrapolated to infinity: “My existing solution has limitations, but the new technology should have no limitations.” Sometimes ex... » read more

Using Machine Learning For Characterizations Of NoC Components
By Arteris - 06 Oct, 2021 - Comments: 0

Modern NoC (Network-on-Chip) is built of complex functional blocks, such as packet switches and protocol converters. PPA (performance/power/area) estimates for these components are highly desirable during early design phases – long before NoC gate level netlist is synthesized. At this stage a NoC component is a soft module, described by a set of architectural parameters, like the bit width of... » read more

NoC Experiences From The Trenches
By Kurt Shuler - 28 Sep, 2021 - Comments: 0

Network-on-chip (NoC) interconnect as an alternative to traditional crossbars is already well-proven, but there are still plenty of design teams on the cusp of a transition or who maybe do not yet see a need for a change. As with a switch to any new technology, the first hurdles are often simply misconceptions. When new users first evaluate any new technology, they often make the mistake of att... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy