In-System Networks Are Front And Center

By Kurt Shuler - 16 Sep, 2019 - Comments: 0

This year’s HotChips conference at Stanford was all about artificial intelligence (AI) and machine learning (ML) and what particularly struck me, naturally because we’re in this business too, was how big a role on-chip networks played in some of the leading talks. NVIDIA talked about their scalable mesh architecture, both on-chip and in-package, meshes connecting processing NN processing el... » read more

5G Design Changes

By Ed Sperling - 07 Jun, 2019 - Comments: 0

Mike Fitton, senior director of strategic planning at Achronix, talks with Semiconductor Engineering about the two distinct parts of 5G deployment, how to get a huge amount of data from the core to the edge of a device where it is usable, and how a network on chip can improve the flow of data. » read more

Speeding Up AI

By Ed Sperling - 06 Jun, 2019 - Comments: 0

Robert Blake, president and CEO of Achronix, sat down with Semiconductor Engineering to talk about AI, which processors work best where, and different approaches to accelerate performance. SE: How is AI affecting the FPGA business, given the constant changes in algorithms and the proliferation of AI almost everywhere? Blake: As we talk to more and more customers deploying new products and... » read more

Interconnect Prominence In Fail-Operational Architectures

By Kurt Shuler - 02 May, 2019 - Comments: 0

When we in the semiconductor world think about safety, we think about ISO 26262, FMEDA and safety mechanisms like redundancy, ECC and lock-step operation. Once we have that covered, any other aspect of safety is somebody else’s problem, right? Sadly no, for us at least. As we push towards higher levels of autonomy, SAE levels 3 and above, we’re integrating more functionality into our SoCs, ... » read more

Memory Architectures In AI: One Size Doesn’t Fit All

By Kurt Shuler - 04 Apr, 2019 - Comments: 0

In the world of regular computing, we are used to certain ways of architecting for memory access to meet latency, bandwidth and power goals. These have evolved over many years to give us the multiple layers of caching and hardware cache-coherency management schemes which are now so familiar. Machine learning (ML) has introduced new complications in this area for multiple reasons. AI/ML chips ca... » read more

The Race To Multi-Domain SoCs

By Ed Sperling - 07 Feb, 2019 - Comments: 0

K. Charles Janac, president and CEO of Arteris IP, sat down with Semiconductor Engineering to discuss the impact of automotive and AI on chip design. What follows are excerpts of that conversation. SE: What do you see as the biggest changes over the next 12 to 24 months? Janac: There are segments of the semiconductor market that are shrinking, such as DTV and simple IoT. Others are going ... » read more

Using Memory Differently

By Ann Mutschler - 31 Jan, 2019 - Comments: 0

Chip architects are beginning to rewrite the rules on how to choose, configure and use different types of memory, particularly for chips with AI and some advanced SoCs. Chipmakers now have a number of options and tradeoffs to consider when choosing memories, based on factors such as the application and the characteristics of the memory workload, because different memory types work better tha... » read more

AI Chips: NoC Interconnect IP Solves Three Design Challenges

By Kurt Shuler - 10 Jan, 2019 - Comments: 0

New network-on-chip (NoC) interconnect IP is now available for artificial intelligence (AI) systems-on-chip (SoC). Arteris IP launched the fourth generation of the FlexNoC interconnect IP with a new optional AI package. The novel NoC interconnect technologies solves many data flow problems in today’s AI designs. Innovative features address the requirements of the next-generation of AI chips t... » read more

Beyond The RISC-V ISA

By Gajinder Panesar - 20 Dec, 2018 - Comments: 1

For chip architects and designers today, “the ISA” in RISC-V is a small consideration. The concern isn’t even choosing “the core.” Designers today are faced by a “whole system” problem—a problem of systemic complexity. That fact is implicit in the picture that I show people to explain the UltraSoC embedded analytics architecture. It shows a block-level representation of an So... » read more

Week in Review: IoT, Security, Auto

By Jeff Dorsch - 05 Oct, 2018 - Comments: 0

Internet of Things Amazon Web Services announced that Iridium Communications has joined the AWS Partner Network. AWS and Iridium have collaborated on development of Iridium CloudConnect, a service that enables worldwide coverage for Internet of Things applications through Iridium’s satellite network. AWS IoT is being paired with Iridium IoT services as a result. IHS Markit forecasts there wi... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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