What’s Next?


We just concluded two very successful seminars in Tokyo and Shanghai. Samsung Memory presented their HBM2 solutions, Samsung Foundry talked about their advanced 14nm FinFET solutions, ASE Group reviewed their advanced 2.5D packaging solutions, eSilicon presented our ASIC and 2.5D design/implementation and IP solutions, Rambus detailed their high-performance SerDes solutions and Northwest Logic ... » read more

Mixing Interface Protocols


Continuous and pervasive connectivity requires devices to support multiple interface protocols, but that is creating problems at multiple levels because each protocol is based on a different set of assumptions. This is becoming significantly harder as systems become more heterogeneous and as more functions are crammed into those devices. There are more protocols that need to be supported to ... » read more

The Week In Review: Design


Tools Imperas debuted its RISC-V Processor Developer Suite, a set of models, a software simulator, and tools to validate, verify, and provide early estimation of timing performance and power consumption for RISC-V processors. IP Minima Processor revealed its dynamic-margining subsystem IP for near-threshold voltage design. The startup's hardware and software IP works with a CPU or DSP proc... » read more

The Week In Review: Design


M&A Silvaco finalized its acquisition of SoC Solutions. The Georgia-based company was founded in 2000. Its team and portfolio of pre-configured IP subsystems and IoT/M2M IP will join Silvaco's IP group. Terms were not disclosed. Siemens PLM will acquire TASS International, a provider of simulation software, engineering and test services aimed primarily at the automotive industry. Based ... » read more

Start Your HBM/2.5D Design Today


High-bandwidth memory (HBM) is a JEDEC-defined standard, dynamic random access memory (DRAM) technology that uses through-silicon vias (TSVs) to interconnect stacked DRAM die. In its first implementation, it is being integrated with a system-on-chip (SoC) logic die using 2.5D silicon interposer technology. In June 2015, AMD introduced its Fiji processor, the first HBM 2.5D design, which comp... » read more

The Week In Review: Design


Tools Synopsys updated RSoft, its software for the design of photonic devices. The updates include increased integration with the company's TCAD products as well as faster simulations and additional ways to customize photonic device analysis. IP Mentor Graphics, Northwest Logic, and Krivi Semiconductor collaborated on DDR4 SDRAM IP to integrate design and verification into a single flo... » read more

High-Bandwidth Memory


High-bandwidth memory (HBM) is a JEDEC-defined standard, dynamic random access memory (DRAM) technology that uses through-silicon vias (TSVs) to interconnect stacked DRAM die. In its first implementation, it is being integrated with a system-on-chip (SoC) logic die using 2.5D silicon interposer technology. This white paper explains HBM’s value proposition, and how these five companies make... » read more

The Week In Review: Design/IoT


M&A Mentor Graphics acquired the rest of Calypto. In 2011, Mentor sold Calypto their high-level synthesis solution – Catapult – in exchange for 51% of the company, but left it as a fully standalone entity. Calypto will now be merged into Mentor as a standalone business unit. Tools Synopsys released its HAPS-80 FPGA-based prototyping system. According to Synopsys, the system pro... » read more

Architecting For Optimal Interface IP Integration


Semiconductor Engineering sat down to discuss the design and integration of complex interface IP with Ty Garibay, vice president of engineering at [getentity id="22849" e_name="Altera"]; Brian Daellenbach, president of Northwest Logic; Frank Ferro, senior director of product management for memory and interface IP at [getentity id="22671" e_name="Rambus"]; Saman Sadr, director of analog design... » read more

Architecting For Optimal Interface IP Integration


Semiconductor Engineering sat down to discuss the design and integration of complex interface [getkc id="43" comment="IP"] with Ty Garibay, VP of engineering at Altera; Brian Daellenbach, president of Northwest Logic; Frank Ferro, senior director of product management for memory and interface IP at [getentity id="22671" e_name="Rambus"]; Saman Sadr, director of analog design at Semtech; and Nav... » read more

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