Technical Paper Roundup: November 14


New technical papers added to Semiconductor Engineering’s library this week. [table id=165 /] More Reading Technical Paper Library home » read more

CMOS-Based HW Topology For Single-Cycle In-Memory XOR/XNOR Operations


A technical paper titled “CMOS-based Single-Cycle In-Memory XOR/XNOR” was published by researchers at University of Tennessee, University of Virginia, and Oak Ridge National Laboratory (ORNL). Abstract: "Big data applications are on the rise, and so is the number of data centers. The ever-increasing massive data pool needs to be periodically backed up in a secure environment. Moreover, a ... » read more

Using Deep Learning to Secure The CAN Bus From Advanced Intrusion Attacks


A technical paper titled “CANShield: Deep Learning-Based Intrusion Detection Framework for Controller Area Networks at the Signal-Level” was published by researchers at Virginia Tech and others. "As modern vehicles become more connected to external networks, the attack surface of the CAN bus system grows drastically. To secure the CAN bus from advanced intrusion attacks, we propose a sig... » read more

Week In Review: Auto, Security, Pervasive Computing


The Biden-Harris Administration announced the U.S. Cyber Trust Mark, a cybersecurity certification and labeling program to help consumers choose smart devices less vulnerable to cyberattacks. The Federal Communications Commission (FCC) is applying to register the Cyber Trust Mark with the U.S. Patent and Trademark Office and it would appear on qualifying smart products, including refrigerators,... » read more

Chip Industry’s Technical Paper Roundup: June 13


New technical papers recently added to Semiconductor Engineering’s library: [table id=109 /] Further Reading Technical Paper Home » read more

High Performance, Energy-Dense, Practical, And Reliable Solid-State Batteries (ORNL)


A technical paper titled “Tailoring of the Anti-Perovskite Solid Electrolytes at the Grain-Scale” was published by researchers at Oak Ridge National Laboratory. Abstract: "The development of thin, dense, defect-free solid electrolyte films is key for achieving practical and commercially viable solid-state batteries. Herein, we showcase a facile processing pathway for antiperovskite (Li2OH... » read more

Week In Review: Design, Low Power


Cadence bought Pulsic, a U.K.-based developer of place-and-route tools for custom digital and analog. The acquisition follows a previous acquisition attempt by a Chinese firm in August 2022, which was blocked by the U.K. government. At the G7 Summit in Japan, IBM announced a 10-year, $100 million initiative with the University of Tokyo and the University of Chicago to develop a quantum-centr... » read more

Research Bits: May 10


Growing 2D TMDs on chips Researchers from Massachusetts Institute of Technology (MIT), Oak Ridge National Laboratory, and Ericsson Research found a way to “grow” layers of 2D transition metal dichalcogenide (TMD) materials directly on top of a fully fabricated silicon chip, a technique they say could enable denser integrations. The researchers focused on molybdenum disulfide, which is f... » read more

Chip Industry’s Technical Paper Roundup: May 8


New technical papers recently added to Semiconductor Engineering’s library: [table id=102 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us... » read more

Week In Review: Design, Low Power


Arm and Intel Foundry Services inked a multi-generation agreement to enable chip designers to build Arm-based SoCs on the Intel 18A process. The initial focus is mobile SoC designs, but the deal allows for potential expansion into automotive, IoT, data center, aerospace, and government applications. IFS and Arm will undertake design technology co-optimization (DTCO) to optimize chip design and ... » read more

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