tag: Open-Silicon

The Impact of Moore’s Law Ending
By Brian Bailey - 29 Oct, 2018 - Comments: 2

Over the past couple of process nodes the chip industry has come to grips with the fact that Moore's Law is slowing down or ending for many market segments. What isn't clear is what comes next, because even if chipmakers stay at older nodes they will face a series of new challenges that will drive up costs and increase design complexity. Chip design has faced a number of hurdles just to get ... » read more

Pushing Performance Limits
By Brian Bailey - 08 Feb, 2018 - Comments: 0

Trying to squeeze the last bit of performance out of a chip sounds like a good idea, but it increases risk and cost, extends development time, reduced yield, and it may even limit the environments in which the chip can operate. And yet, given the amount of margin added at every step of the development process, it seems obvious that plenty of improvements could be made. "Every design can be o... » read more

The Week In Review: Design
By Jesse Allen - 17 Nov, 2017 - Comments: 0

Tools Aldec released the latest version of its Riviera-PRO verification platform, adding QEMU Bridge to enable hardware/software co-simulation of designs intended to run on SoC FPGAs. Other features include improved performance when using code containing many inline randomized calls and up to 29% faster simulation speed of UVM. Pulsic added new features to its Unity Bus Planner for planning... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 10 Nov, 2017 - Comments: 0

Packaging and test A*STAR’s Institute of Microelectronics (IME) has formed a fan-out wafer-level packaging consortium comprising of OSATs, materials vendors, equipment suppliers and others. The group is called the FOWLP Development Line Consortium. As part of the announcement, Singapore’s IME has established a development line to accelerate the development of fan-out. Located in IME’s... » read more

The Week In Review: Design
By Jesse Allen - 15 Sep, 2017 - Comments: 0

Tools Cadence unveiled a new equivalence checking tool which features a massively parallel architecture capable of scaling to 100s of CPUs and adaptive proof technology that analyzes each partition and determines the optimal formal algorithm. According to the company, the Conformal Smart Logic Equivalence Checker provides an average of 4X runtime improvement with the same resources over the pr... » read more

Hybrid Emulation
By Brian Bailey - 19 Jul, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for [getentity id="22032" e_name="Cadence"]; Russ Klein, program director for pre-silicon debug products at [getentity id="22017" e_name="Mentor, a Siemens Business"]; [getperson id="11027" comment="Phil Moorby"],... » read more

Hybrid Emulation
By Brian Bailey - 29 Jun, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for [getentity id="22032" e_name="Cadence"]; Russ Klein, program director for pre-silicon debug products at [getentity id="22017" e_name="Mentor, a Siemens Business"]; [getperson id="11027" comment="Phil Moorby"],... » read more

Monday At DAC
By Brian Bailey - 20 Jun, 2017 - Comments: 1

The 54th DAC got started today in a very steamy Austin. While we may be a maturing industry, there is certainly no indications that the people within the industry have given up or intend to take it easy. The event really got started late Sunday when Laurie Balch, chief analyst for Gary Smith EDA, delivered her message. She said that the focus is becoming the verticals. "This change in focus is ... » read more

The Week In Review: Design
By Jesse Allen - 07 Apr, 2017 - Comments: 0

Name Changes Arteris changed its name to ArterisIP. The company said the name change better reflects what the company does, which is provide IP for SoC communication on-die and between die. Mentor Graphics also modified its name, following last week's announcement that the acquisition by Siemens has been completed. The company is now officially called Mentor, A Siemens Business. It also ... » read more

CEO Outlook: Chip Design 2017
By Ed Sperling - 22 Dec, 2016 - Comments: 0

After two consecutive flat to slightly down years, the semiconductor industry is poised for growth in 2017. Cowan this month predicted 4.7% growth in semiconductor sales in 2017, while World Semiconductor Trade Statistics (WSTS) put that figure at 3.3%. And last month, International Business Strategies (IBS) pegged the number at 4.6%, according to statistics compiled by the Global Semiconduc... » read more

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