tag: Open-Silicon

FD-SOI Meets The IoT
By Ann Mutschler - 05 Feb, 2015 - Comments: 1

Silicon-on-insulator manufacturing technology has been discussed for many years. IBM has used the partially depleted variation of SOI in its server products, but the fully depleted version has yet to find widespread adoption outside of mil/aero and automotive markets. That may change soon as applications in the Internet of Things ramp, given the requirements for ultra low power and low cost.... » read more

Blog Review: Feb. 4
By Jesse Allen - 04 Feb, 2015 - Comments: 0

After the Super Bowl, Ansys' Thierry Marchal looks at making football safer through virtual prototyping. Sports concussions are a serious danger for athletes from youths to professionals, and modeling head and brain impacts may lead not only to safer football helmets but a better understanding of how to lower the chance of brain injuries in sports. Synopsys' Ray Varghese continues his series... » read more

Back To The Future
By Ed Sperling - 02 Feb, 2015 - Comments: 0

The push to the next process node typically has meant that designs get simpler at existing and older nodes because the process technology is more mature and there have been so many chips developed at those nodes—many billions of them—that every possible corner case has been encountered hundreds, if not thousands, of times. That all makes sense in theory, but several key things have chang... » read more

First Look: 10nm
By Ed Sperling - 29 Jan, 2015 - Comments: 6

As the semiconductor industry begins grappling with mass production at 14/16nm process nodes, work is already underway at 10nm. Tools are qualified, IP is characterized, and the first test chips are being produced. It's still too early for production, of course—perhaps three years too early—but there is enough information being collected to draw at least some impressions about just how toug... » read more

Speeding Up Timing Constraint Creation, Refinement And Validation
By Divya Macharla - 29 Jan, 2015 - Comments: 0

We are dealing with designs integrating many features and working with cutting-edge process technologies. Design methodologies and the design and process complexities can be overwhelming. To leverage the advancements in EDA tools and to achieve optimal power, performance and area results while overcoming design complexities, it is important to have a qualitative timing constraint file that c... » read more

Blog Review: Dec. 31
By Ed Sperling - 31 Dec, 2014 - Comments: 0

Mentor's J. VanDomelen zeroes in on the two most interesting discoveries from the Philae comet landing. So what was that "eerie cyclical clicking" sound? Synopsys' Ray Varghese digs into basic coherent transaction testing for AXI/ACE compliant interconnects. You might want to put on another pot of coffee. Cadence's Brian Fuller offers some deep insights into synthesis, verification and te... » read more

Is The Stacked Die Ecosystem Stagnating?
By Ann Mutschler - 23 Dec, 2014 - Comments: 0

While the stacked die ecosystem in general is currently status quo, with not much happening in the past year, there is definitely work being done —albeit cautiously—on the design tools side of things. It would be easy to feel impatient that the design tools are not complete and available today for [getkc id="82" comment="2.5D"] and [getkc id="42" comment="3D IC"] implementation until hearin... » read more

Trouble Spots And Optimism For 2015
By Ed Sperling - 18 Dec, 2014 - Comments: 0

Most top executives in the semiconductor industry are bullish about 2015 and even beyond, particularly as the [getkc id="76" comment="Internet of Things"] begins to drive new markets and market mash-ups, and as more semiconductors find their way into markets such as automotive, health-care and manufacturing. But it's not an entirely rosy picture, and top executives point to potential trouble sp... » read more

Is The Stacked Die Ecosystem Stagnating?
By Ann Mutschler - 18 Dec, 2014 - Comments: 2

It is now widely agreed that not much has been happening in terms of adoption for 2.5D interposer and 3D ICs. “It seems like everyone is still at the starting line waiting for the race to begin," said Javier DeLaCruz, senior director of engineering of [getentity id="22242" e_name="eSilicon"]. "Interposer assembly and IP availability for effectively using the [getkc id="82" comment="2.5D IC... » read more

Manufacturing Constraint Fears Grow
By Ed Sperling - 18 Dec, 2014 - Comments: 0

The semiconductor industry could become a victim of its own success. With so many semiconductors being consumed inside of cars, home electronics and industry, capacity shortages are beginning to surface in some areas. Foundries set rates depending upon a complex mix of process technology, equipment depreciation, customer demand and the need to push customers from one node the next depending ... » read more

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