Is The Stacked Die Ecosystem Stagnating?

Second of two parts: It is no easy task to create or adapt tools for the 2.5D/3D world. The challenges are many.

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While the stacked die ecosystem in general is currently status quo, with not much happening in the past year, there is definitely work being done —albeit cautiously—on the design tools side of things. It would be easy to feel impatient that the design tools are not complete and available today for 2.5D IC and 3D ICs implementation until hearing of the new complexities they must address.

While asserting that the EDA ecosystem is not fully ready to do a 2.5D or 3D design, Radhakrishnan Pasirajan, vice president of engineering at Open-Silicon, also points out a number of challenges those tools must address at every stage of a 2.5D design.

“When you talk about the die, the approach for die that is to be used in an interposer should be almost like a true area-I/O kind of implementation. You can do a non-area-I/O implementation but the effectiveness of the TSVs comes when you actually use a true area-I/O implementation. There are other things like verifying the timing, extracting the timing model of the dies when the interposers are in place because they are all going to a different technology mismatches, impedance mismatches, signal integrity effects — a lot of those things will come,” Pasirajan said.

Other problems exist with power yield and the thermal modeling of the entire die, Pasirajan continued. “These are the complexities that today we solve in pieces. We know that we have done one die, we have done another die, we know that these are to be interacting. There are, say, 2,000 lines that are connecting between the two. If we can do a SPICE analysis or maybe a very close timing modeling analysis to integrate all of that to make sure that the interface is isolated from synchronous transfers—these are some ideas that we have used to make sure that this design is implementable in a 2.5D solution. But that kind of EDA environment where you can simply say, here are my three dies, these are the interfaces, these are the constraints at the top level, let’s just go do the timing analysis, just go do the extraction — tools have not come to that level so we have to fracture each of the pieces and solve them separately and build it by design to make it work. That’s how we approach the problem.”

This is no small task. Open-Silicon has been working on this for two years to make sure that the interface was designed in such a way that there is not too much of a dependency in the timing closure in each of the dies, so the I/Os are relatively isolated from the timing impacts, he explained.

As we move forward, this will change. Slowly the tools will be extended to the next level of abstraction and then it will be part of the die analysis. Those kind of evolutions are expected in the next year or two. And if there are design wins, the EDA tool companies will wake up and the tools will be made ready, Pasirajan added.

To this end, Si2’s 3D Technical Advisory Board is working on some standards to streamline the process. According to Herb Reiter, president of eda2asic Consulting and director of 3D-IC programs at Si2, the manufacturers are getting to a maturity point where they are doing reliability analysis and getting ready to generate design kits. Today, design tools for 3D-ICs are good for particular steps in the design process, but what is really needed to make IC and system designers comfortable with this new technology is a soup-to-nuts environment that spans planning to tapeout.

So far, IBM, Intel, AMD, Qualcomm, TI, STMicroelectronics and other systems companies are participating on the advisory board to enable such a design flow because it makes the designers’ efforts more efficient, and more promising in regard to meeting schedules and cost/performance targets. At the same, it will make all the EDA players that are right now pursing this particular market segment compatible. Data exchange formats will be defined so that if a chip designer is using a very good planning tool from one vendor and wants to continue with another vendor’s tool for verification, this will be possible because the tools will know a common language and can communicate with each other, he said.

“A key goal we are working on with the manufacturing side is to bring in assembly-related information into the design flow, as well, including whatever information is needed to make the design manufacturable,” Reiter added.

Will it really work?
Drew Wingard, CTO of Sonics said he is particularly worried about designer rules, electrical rules, and electrical characterization. “How do I make sure I understand what I can expect to be the real electrical characteristics equivalent of the SPICE model or the die to bump to interposer through trace to next bump and into the next die? How do I effectively analyze that chain? Maybe more importantly, you need to understand the yield and corner models of those because it’s one thing to get what the nominal values are. But we’re talking about it being designed around a set of quasi worst case constraints. What are the corner models? What does the slow model look like for this? What does the fast model look like? And then we’re integrating that together with the rest of the design database information so that I could begin to think about communicating between two die using something other than a physical layer.”

Right now there seem to be two camps of engineering teams approaching 2.5D designs, according to Bill Acito, Jr., product engineering technologist for IC packaging at Cadence. “There’s a camp that looks at these designs from purely an IC design perspective. A good example of this is the Xilinx Virtex-7. That was a means to integrate a group of cores together using a silicon interposer effectively as top layers of metal. That’s clearly an IC design problem and challenge. We also have a group of customers where the interposer-type integration has been put on the packaging guys as the mechanism to do this, and not the IC group. They look at it from a different perspective. What these designers are doing is using our packaging tools to prototype, to analyze, to do the initial layout — to basically put these systems together, and then transition over to an IC tool to do final artwork before they go off to mask making for the design.”

It seems like it would be simpler to have a single tool for 2.5D designs, but Keith Felton, product management for IC packaging at Cadence, pointed out that it depends on the processes and methodologies that the engineering teams want to implement the interposer design in.

“We have some of our customers that are very fab-centric and want to do this in an IC process, so they want to do some of the initial planning within the chip tools,” Felton said. “You normally find design engineers don’t like to change tools, don’t like to use different methodologies, so if the driving force or responsibility is the IC design team who are creating the chip, they want to integrate that with one or more other chips. They tend to want to do it in their tool environment, at least for the initial planning and verification. And they can be doing that from a digital perspective, maybe they’re doing a digital top-down approach, or they may be doing a mixed-signal type of chip and there are two different ways of implementing it. They will tend to do it in their native environments. At some point, they need to hand off to a packaging design person because they have to then take that interposer, integrate it into the package, into the BGA usually, and ensure that the interconnect parts are optimized, not just with connectivity, layout optimization, but signal and power integrity. This will help ensure a stable power delivery network from the PCB, where it will eventually get mounted through the package, then supplying power up to the interposer, and then up on into the multiple die.”

Further, he noted that if looking at this from a pure 3D-IC integration perspective, using through silicon vias, for example, that still tends to be limited to the memory guys who do that.

“There are other players that do it where they are in full control of the dies they wish to mount together because you can’t just take two disparate die and suddenly decide you’re going to jam them together with TSVs,” he said. “You have to make sure that the lowest die can supply adequate power to the upper die. You don’t want to have areas of circuitry that creates a lot of noise about another area of circuitry, so you want to design the floor plan with that perspective in mind. A lot of people were initially thinking that you could go out there tomorrow, take your SoC, pick up a couple of other devices like a memory controller, some other type of device, and miraculously remanufacture the wafers and join them all together with TSVs. And people have done some experiments, but usually the yield and the process is prohibitive for that. You really can’t justify it. That’s why people have migrated more to the 2.5D interposer approach, because if they use a silicon interposer they keep in a very similar environment in terms of characteristic impedance, signal performance properties, and they also keep it relatively small.”

At the end of the day, whether it is IoT or handheld wireless devices or automotive applications that set the stage and truly propel 2.5D and 3D design starts, there are technical challenges to overcome. How soon they are solved within the EDA tools ecosystem is anyone’s guess, but it is should be fascinating to see the solutions emerge.