tag: optical critical dimension

Using OCD To Measure Trench Structures In SiC Power Devices
By Nick Keller - 08 Feb, 2024 - Comments: 0

You don’t have to be a dedicated follower of the transportation industry to know it is in the early stages of a significant transition, away from the rumbling internal combustion engine to the quiet days of electric vehicles. The signs of this transition are right there on the streets in the form of electric-powered buses, bikes and cars. The road to our electric future is before us, but we w... » read more

Navigating the Metrology Maze For GAA FETs
By Gregory Haley - 08 Aug, 2023 - Comments: 1

The chip industry is pushing the boundaries of innovation with the evolution of finFETs to gate-all-around (GAA) nanosheet transistors at the 3nm node and beyond, but it also is adding significant new metrology challenges. GAA represents a significant advancement in transistor architecture, where the gate material fully encompasses the nanosheet channel. This approach allows for the vertical... » read more

A New Dimension In Optical CD
By Ilya Osherov - 15 Dec, 2022 - Comments: 0

One of the biggest challenges for nanoscale fabrication is how to measure devices on such a minute scale. As the semiconductor industry demands ever smaller devices, the need for reliable, robust measurements for quality control and process optimization increases. One robust and commonly used technique in semiconductor manufacturing is optical critical dimension (OCD) metrology. Standard, al... » read more

Using BDA To to Predict SAQP Pitch Walk
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A new technical paper titled "Bayesian dropout approximation in deep learning neural networks: analysis of self-aligned quadruple patterning" was published by researchers at IBM TJ Watson Research Center and Rensselaer Polytechnic Institute. Find the technical paper here. Published November 2022.  Open Access. Scott D. Halle, Derren N. Dunn, Allen H. Gabor, Max O. Bloomfield, and Mark Sh... » read more

Methods To Overcome Limited Labeled Data Sets In Machine Learning-Based Optical Critical Dimension Metrology
By Onto Innovation - 07 Sep, 2022 - Comments: 0

With the aggressive scaling of semiconductor devices, the increasing complexity of device structure coupled with tighter metrology error budget has driven up Optical Critical Dimension (OCD) time to solution to a critical point. Machine Learning (ML), thanks to its extremely fast turnaround, has been successfully applied in OCD metrology as an alternative solution to the conventional physical... » read more

Nanosheet FETs Drive Changes In Metrology And Inspection
By Karen Heyman - 09 Aug, 2022 - Comments: 0

In the Moore’s Law world, it has become a truism that smaller nodes lead to larger problems. As fabs turn to nanosheet transistors, it is becoming increasingly challenging to detect line-edge roughness and other defects due to the depths and opacities of these and other multi-layered structures. As a result, metrology is taking even more of a hybrid approach, with some well-known tools moving... » read more

The Human Hand: Curating Good Data And Creating An Effective Deep-Learning R2R Strategy For High-Volume Manufacturing
By Onto Innovation - 09 Aug, 2022 - Comments: 0

Currently, the semiconductor manufacturing industry uses artificial intelligence and machine learning to take data and autonomously learn from that data. With the additional data, AI and ML can be used to quickly discover patterns and determine correlations in various applications, most notably those applications involving metrology and inspection, whether in the front-end of the manufacturing ... » read more

Can We Measure Next-Gen FinFETs?
By Mark LaPedus - 21 Nov, 2016 - Comments: 6

After ramping up their respective 16nm/14nm finFET processes, chipmakers are moving towards 10nm and/or 7nm, with 5nm in R&D. But as they move down the process roadmap, they will face a new set of fab challenges. In addition to lithography and interconnects, there is metrology. Metrology, the science of measurements, is used to characterize tiny films and structures. It helps to boost yi... » read more

Getting Over Overlay
By Mark LaPedus - 18 Jun, 2015 - Comments: 0

Chipmakers continue to migrate to the next node, but there are signs that traditional IC scaling is slowing down. So what’s causing the slowdown? Or for that matter, what could ultimately undo [getkc id="74" comment="Moore's Law"]? It could be a combination of factors. To be sure, IC design costs and complexity are soaring at each node. Scaling challenges are also playing a role. And ov... » read more

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