tag: overlay

3D Metrology Meets Its Match In 3D Chips And Packages
By Laura Peters - 11 Jun, 2024 - Comments: 0

The pace of innovation in 3D device structures and packages is accelerating rapidly, driving the need for precise measurement and control of feature height to ensure these devices are reliable and perform as expected throughout their lifetimes. Expansion along the z axis is already well underway. One need look no further than the staircase-like 3D NAND stacks that rise like skyscrapers to p... » read more

Overlay Optimization In Advanced IC Substrates
By Ed Sperling - 29 Apr, 2024 - Comments: 1

Overlay is becoming a significant problem in the manufacturing of semiconductors, especially in the world of advanced packaging substrates — think panels — the larger the area, the greater the potential for distortion due to warpage. Solving this issue requires more accurate models, better communication through feed forward/feed back throughout the flow, and real-time analytics that are bak... » read more

Total Overlay With Multiple RDLs
By Ed Sperling - 13 Nov, 2023 - Comments: 0

As Advanced IC Substrates (AICS) add more RDL layers, requiring additional via connections between the RDL layers, the potential for cumulative overlay shift increases. This overlay shift can lead to longer RDL traces, which increases interconnect resistance, resulting in lower yield. Keith Best, director of product marketing, for lithography at Onto Innovation, talks about total overlay — th... » read more

Addressing Total Overlay Drift In Advanced IC Substrate (AICS) Packaging
By Keith Best - 07 Mar, 2023 - Comments: 0

For years, many in the semiconductor industry have focused on the march toward advanced nodes. As these nodes have decreased in size, the size of input/output (I/O) bumps on the chip has grown smaller. As these bumps shrink, their ability to mate directly to printed circuit boards (PCB) diminishes, which, in turn, leads to the need for an intermediary substrate. Enter the advanced IC substrate ... » read more

Heterogeneous Integration: Correcting Overlay Errors On Advanced Integrated Circuit Substrates (AICS)
By John Chang - 08 Nov, 2022 - Comments: 0

By John Chang, with Corey Shay, James Webb, and Timothy Chang For high-performance computing, artificial intelligence, and data centers, the path ahead is certain, but with it comes a change in substrate format and processing requirements. Instead of relying on the quest for the next technology node to bring about future device performance gains, manufacturers are charting a future based inc... » read more

Heterogeneous Integration: Exposing Large Panels With Fewer Shots
By John Chang - 11 Oct, 2022 - Comments: 0

By John Chang, with Corey Shay, James Webb, and Timothy Chang The More than Moore era is upon us, as manufacturers increasingly turn to back-end advances to meet the next-generation device performance gains of today and tomorrow. In the advanced packaging space, heterogeneous integration is one tool helping accomplish these gains by combining multiple silicon nodes and designs inside one pac... » read more

How Overlay Keeps Pace With EUV Patterning
By Laura Peters - 09 Aug, 2022 - Comments: 1

Overlay metrology tools improve accuracy while delivering acceptable throughput, addressing competing requirements in increasingly complex devices. In a race that never ends, on-product overlay tolerances for leading-edge devices are shrinking rapidly. They are in the single-digit nanometer range for the 3nm generation (22nm metal pitch) devices. New overlay targets, machine learning, and im... » read more

New Method For BEOL Overlay And Process Margin Characterization
By PDF Solutions - 07 Jun, 2022 - Comments: 0

This paper presents a new method, design for inspection (DFI) to characterize overlay. Using design-assisted voltage contrast measurement, the method enables in-line test and monitoring of process induced OVL and CD variation of backend-of line (BEOL) features with litho-etch-lithoetch (LELE) patterning. While only some of the features of multi-color patterning scheme are chosen to be aligned d... » read more

Imaging Of Overlay And Alignment Markers Under Opaque Layers Using Picosecond Laser Acoustic Measurements
By Onto Innovation - 09 Nov, 2021 - Comments: 0

Optically opaque materials present a series of challenges for alignment and overlay in the semi-damascene process flow or after the processing of the magnetic tunnel junction (MTJ) of a Magnetic Random-Access Memory (MRAM). The overlay and alignment of a lithographically defined pattern on top of the pattern and the underlying layer is fundamental to device operation in all multi-layer patterne... » read more

Extremely Large Exposure Field w/Fine Resolution Lithography Tech To Enable Next-Gen Panel Level Advanced Packaging
By Technical Paper Link - 05 Aug, 2021 - Comments: 0

Abstract—"The growing demand for heterogeneous integration is driven by the 5G market that includes smartphones, data centers, servers, HPC, AI and IoT applications. Next-generation packaging technologies require tighter overlay to accommodate a larger package size with finer pitch chip interconnects on large format flexible panels. Heterogeneous integration enables next-generation device per... » read more

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