How Secure Is The Package?

By Ed Sperling - 17 Sep, 2020 - Comments: 1

Advanced packaging is a viable way of extending the benefits of Moore's Law without the excessive cost of shrinking everything to fit on a single die, but it also raises some issues about security for which there are no clear answers at the moment. OSATs and foundries have been working the kinks out of how to put the pieces together in the most cost-effective and reliable way for the better ... » read more

Early And Fine Virtual Binning

By Noam Brousard - 08 Sep, 2020 - Comments: 0

Not all chips are created equal, and this is viewed as both a blessing and a curse by semiconductor makers. On one hand, chips can be screened for certain attributes, and some of the chips can be sold for higher prices than others. On the other hand, variations in the production process cause silicon performance to greatly differ, leaving chip makers with a wide and somewhat unpredictable distr... » read more

Understanding Advanced Packaging Technologies And Their Impact On The Next Generation Of Electronics

By Sandy Wen - 28 Aug, 2020 - Comments: 2

Chip packaging has expanded from its conventional definition of providing protection and I/O for a discrete chip to encompassing a growing number of schemes for interconnecting multiple types of chips. Advanced packaging has become integral to embedding increased functionality into a variety of electronics, such as cellular phones and self-driving vehicles, by supporting high device density in ... » read more

Make Acute Angles A Sharp Problem Of The Past

By Tyler Lockman - 13 Aug, 2020 - Comments: 0

Sharp angles, whether they create a spike in a poured shape or form an acid trap between two different pieces of metal, are a problem for us all. As designers, we will go out of our way to try and avoid creating these situations; they will still creep into your design despite the best of intentions. How, then, can you efficiently rid your design of them with the minimal change to your routin... » read more

Smaller Nodes, Much Bigger Problems

By Ed Sperling - 15 Jul, 2020 - Comments: 3

João Geada, chief technologist at Ansys, sat down with Semiconductor Engineering to talk about device scaling, advanced packaging, increasing complexity and the growing role of AI. What follows are excerpts of that conversation. SE: We've been pushing along Moore's Law for roughly a half-century. What sorts of problems are you seeing now that you didn't see a couple nodes ago? Geada: The... » read more

Manufacturing Bits: June 30

By Mark LaPedus - 30 Jun, 2020 - Comments: 0

1μm pitch wafer bonding At the recent IEEE Electronic Components and Technology Conference (ECTC), Imec presented a paper on a fine-pitch hybrid wafer-to-wafer bonding technology for heterogeneous integration. Imec described a way to enable hybrid bond pitches down to 1μm using a novel Cu/SiCN (copper/silicon-carbon-nitrogen) surface topography. Today, the industry is developing or shi... » read more

Interconnect Challenges Grow, Tools Lag

By Brian Bailey - 15 Jun, 2020 - Comments: 2

Interconnects are becoming much more problematic as devices shrink and the amount of data being moved around a system continues to rise. This limitation has shown up several times in the past, and it's happening again today. But when the interconnect becomes an issue, it cannot be solved in the same way issues are solved for other aspects of a chip. Typically it results in disruption in how ... » read more

Using Calibre For Advanced IC Packaging Verification And Signoff

By Mentor, a Siemens Business - 10 Jun, 2020 - Comments: 0

As high density advanced package designs evolve and become more common, an automated LVS-like flow to detect and highlight package connectivity errors is required. We explain the most common package verification issues and how designers can resolve them using using Xpedition Substrate Integrator and Calibre 3DSTACK to provide a significant advantage over traditional LVS flows for HDAP. To re... » read more

High-Speed SerDes At 7/5nm

By Ed Sperling - 02 Jun, 2020 - Comments: 0

Manmeet Walia, senior product marketing manager at Synopsys, talks with Semiconductor Engineering about how to optimize PHYs for integration on all four corners of an SoC, as well as the PPA implications of moving large amounts of data across and around a chip. » read more

The Need for Speed

By Subodh Kulkarni - 01 Jun, 2020 - Comments: 0

We’ve previously identified the convergence occurring between surface mount technologies (SMT), used to connect packaged semiconductor devices on printed circuit boards, and advanced packaging (AP) technologies, in which connections between the semiconductor devices and to the outside world are incorporated in the packaging process using front-end-like, wafer-or panel-based manufacturing proc... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

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Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: packaging