Substrates for Semiconductor Packaging

By SEMI - 16 Jan, 2012 - Comments: 0

2012 Market Outlook for Laminate and Leadframe Materials By Jan Vardaman, TechSearch International, and Dan Tracy, SEMI Combined, laminate substrates and leadframes will represent an estimated US$ 13.3 billion market in 2011 and is forecasted to reach $14 billion in 2012. This is larger than the revenues for silicon wafers (including silicon-on-insulator wafers) of $10.3 billion in 2011 and... » read more

Packaging’s Power Play

By Ed Sperling - 13 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler In the not-too-distant past packaging was not an issue IC designers had to think much about. But now, due to smaller geometries and rising complexity, managing power in the entire system has become a major concern for system architects. IC and package designers now must work closely throughout the design process to make sure no surprises come up down the road. A... » read more

What’s With That Big Package?

By Javier DeLaCruz - 23 Sep, 2010 - Comments: 0

By Javier DeLaCruz As SerDes data rates have been going up for years, and 10-Gbps interfaces have been becoming commonplace, I figured a few years ago that pin counts on packages would start going down. Boy, was I wrong on that prediction! The trend instead was to put more of those high-speed interfaces on devices. For years, a 45×45mm body size was really the upper limit on organic f... » read more

3D Integration: Extending Moore’s Law Into The Next Decade

By Cheryl Ajluni - 27 Aug, 2009 - Comments: 0

By Cheryl Ajluni At the 46th Design Automation Conference in San Francisco last month, attention turned to a discussion of how to extend the momentum of Moore’s Law into the next decade. One plausible solution, according to Philippe Magarshack, the general manager of Central CAD & Design Solutions at STMicroelectronics, is 3D stacking for complex System-on-Chips (SoCs). The concept of 3... » read more

The Impact of 3D Packaging

By Ann Mutschler - 11 Jun, 2009 - Comments: 0

With semiconductor packaging becoming a more crucial piece of the Moore’s Law roadmap, the industry is still sorting out the impact of a 3D design and packaging approach on design time, cost and power. 3D is now commonly used for high volume applications such as cell phones and SD cards, and is accomplished at the packaging step either through chip stacking or package-on-package (PoP) stac... » read more

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tag: packaging

Substrates for Semiconductor Packaging

Packaging’s Power Play

What’s With That Big Package?

3D Integration: Extending Moore’s Law Into The Next Decade

The Impact of 3D Packaging