tag: packaging

Semicon West Preview: Packaging
By SEMI - 09 Jun, 2014 - Comments: 0

By Paula Doe The evolving mobile device market means the packaging, assembly and test supply chain faces a growing range of alternative technologies vying for its investment dollar, everything from Google’s modular electronics with 3D printing, to more solutions for integrating varied chips in smaller packaged systems. One potentially disruptive change is the wider use of more open-source... » read more

Improving Yield Of 2.5D Designs
By Ann Mutschler - 18 Apr, 2014 - Comments: 0

While progress is being made on the packaging side of 2.5D design, more needs to be resolved when it comes to improving yields. Proponents of 2.5D present compelling benefits. Arif Rahman, a product architect at Altera, noted that the industry trend of silicon convergence is leading to multiple technologies being integrated into single-chip solutions. “2.5D/3D integration has multiple adva... » read more

More Pain In More Places
By Ed Sperling - 14 Mar, 2014 - Comments: 2

Pain is nothing new in to the semiconductor industry. In fact, the pain of getting complex designs completed on budget, and finding the bugs in those designs, has been responsible for decades of continuous growth in EDA, IP, test, packaging, and foundries. But going forward there is change afoot in every segment of the flow from architecture to design to layout to verification to manufacturi... » read more

Week In Review: System-Level Design
By Ed Sperling - 07 Feb, 2014 - Comments: 0

Cadence agreed to buy Forte Design Systems for an undisclosed sum, adding further proof that the market for high-level synthesis and tools that run at higher levels of abstraction is finally hitting its stride. Behind this acquisition is a rising pain level due to increasing complexity in SoCs—IP integration, low power concerns and much more of everything, from transistors to memories—has f... » read more

Modern IC Packaging
By Various Writers - 18 Dec, 2013 - Comments: 0

Modern IC packaging technologies, such as 3D-IC, drive the need for IC, package and system co-design tools and methodologies. To download this white paper, click here.  » read more

System Bits: Dec. 10
By Brian Bailey - 10 Dec, 2013 - Comments: 0

Lasers From Nano Wires A few weeks ago, Semiconductor Engineering published a special report about silicon photonics and concentrated on the integration of the laser onto the silicon surface. Growing III-V materials on silicon is problematic because of the lattice mismatch, but researchers at the Technische Universität München (TUM) may have found a way around that problem. Thread-like semic... » read more

Tech Talk: 2.5D Stacked Die
By Ed Sperling - 20 Nov, 2013 - Comments: 0

What's the motivation for moving to 2.5D packaging and architectures rather than following Moore's Law? Shafy Eltoukhy, VP of operations and technology development at Open-Silicon, talks with Semiconductor Engineering about adding another dimension in semiconductors. [youtube vid=HwpY9bUNt0w] » read more

Front End Comes To The Back End
By Jeff Chappell - 19 Sep, 2013 - Comments: 0

By Jeff Chappell For outsourced assembly and test (OSAT) houses either planning for or already offering through-silicon via (TSV) capability for their 3D packaging efforts, this has meant the front end is coming to the back end, in a manner of speaking. A bit of an exaggeration perhaps, as most generalizations are. But thanks to TSVs, in a very real sense some of what would typically be the... » read more

3D IC Supply Chain: Still Under Construction
By Barbara Jorgensen - 25 Jul, 2013 - Comments: 1

By Barbara Jorgensen and Ed Sperling Stacked die, which promise high levels of integration, a tiny footprint, energy conservation and blinding speed, still have some big hurdles to overcome. Cost, packaging and manufacturability continue to make steady progress, with test chips being produced by all of the major foundries. But in a disaggregated ecosystem, the supply chain remains a big st... » read more

Foundry Talk
By Ed Sperling - 07 Jul, 2013 - Comments: 0

GlobalFoundries CEO Ajit Manocha sounds off on Foundry 2.0, 450mm wafers, lithography challenges, stacked die, the Internet of Things and the rush to the next process node. [youtube vid=WfjtlZkCi0w] » read more

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